參數(shù)資料
型號(hào)： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 4/152頁
文件大?。?/td> 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
101 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
PTD if the HCD has reset its corresponding skipped bit to logic 0. Clearing the
corresponding bit in the HcINTLPTDSkipMap register when there is no valid data in the
block will cause unpredictable behavior of the Host Controller.
Code (Hex): 18 — read
Code (Hex): 98 — write
14.8.6 HcINTLLastPTD register (R/W: 19h/99h)
This is a 32-bit register, and Table 92 shows its bit description. Bit 0 of the register
represents the rst PTD stored in the INTL buffer, bit 1 represents the second PTD stored
in the buffer, and so on. The bit that is set to logic 1 by the HCD is used as an indication to
the Host Controller that its corresponding PTD is the last PTD stored in the INTL buffer.
When the processing of the last PTD is complete, the Host Controller proceeds to process
ATL transactions.
Code (Hex): 19 — read
Code (Hex): 99 — write
14.8.7 HcINTLCurrentActivePTD register (R: 1Ah)
This register indicates which PTD stored in the INTL buffer is currently active and is
updated by the Host Controller. The HCD can use it as a buffer pointer to decide which
PTD locations are currently free to ll in new PTDs to the buffer. This indication is to
prevent the HCD from accidentally writing into the currently active PTD buffer location.
Table 93 shows the bit allocation of the register.
Code (Hex): 1A — read only
Table 91.
HcINTLPTDSkipMap register: bit description
Bit
Symbol
Access
Value
Description
31 to 0
SkipBits[31:0] R/W
0000h
0 — The Host Controller processes the PTD.
1 — The Host Controller skips processing the PTD.
Table 92.
HcINTLLastPTD register: bit description
Bit
Symbol
Access
Value
Description
31 to 0 LastPTDBits[31:0]
R/W
0000h
0 — The PTD is not the last PTD stored in the buffer.
1 — The PTD is the last PTD stored in the buffer.
Table 93.
HcINTLCurrentActivePTD register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
--------
Access
--------
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
ActivePTD[4:0]
Reset
-
00000
Access
-
RRRRR
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