參數(shù)資料
型號(hào)： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 152/152頁
文件大?。?/td> 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
99 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
14.8 Interrupt transfer registers
14.8.1 HcINTLBufferSize register (R/W: 33h/B3h)
This register allows you to allocate the size of the INTL buffer to be used for interrupt
transactions. The default value of the buffer size is set to 128 bytes, and the maximum
allowable allocated size is 4096 bytes. Table 86 shows the bit description of the register.
Code (Hex): 33 — read
Code (Hex): B3 — write
14.8.2 HcINTLBufferPort register (R/W: 43h/C3h)
In addition to the HcDirectAddressData register, the ISP1362 provides this register to act
as another data port to access the INTL buffer. The starting address to access the buffer
is always xed at 0000h. Therefore, random access of the INTL buffer is not allowed. The
bit description of the HcINTLBufferPort register is given in Table 87.
Code (Hex): 43 — read
Code (Hex): C3 — write
The HCD is rst required to initialize the HcTransferCounter register with the byte count to
be transferred and check the HcBufferStatus register. The HCD then sends the command
(43h to read the INTL buffer, and C3h to write to the INTL buffer) to the Host Controller
through the I/O port of the microprocessor. After the command is sent, the HCD starts
reading data from the INTL buffer or writing data to the INTL buffer. While the HCD is
accessing the buffer, the buffer pointer of INTL also automatically increases. When the
pointer has reached the initialized byte count of the HcTransferCounter register, the Host
Controller sets the AllEOTInterrupt bit of the Hc
PInterrupt register to logic 1 and updates
the HcBufferStatus register.
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
ISTLToggleRate[3:0]
Reset
----
0000
Access
----
R/W
Table 85.
HcISTLToggleRate register: bit description
Bit
Symbol
Description
15 to 4
-
reserved
3 to 0
ISTLToggleRate[3:0]
The required toggle rate in ms.
Table 86.
HcINTLBufferSize register: bit description
Bit
Symbol
Access
Value
Description
15 to 0
INTLBufferSize[15:0] R/W
0080h
The size of the buffer to be used for interrupt transactions and must
be specied in bytes.
Table 87.
HcINTLBufferPort register: bit description
Bit
Symbol
Access
Value
Description
15 to 0
DataWord[15:0]
R/W
0000h
Data in the INTL buffer to be accessed through this data port.
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