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| 型號(hào)： | ISP1362EE,551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64 |
| 文件頁(yè)數(shù)： | 106/152頁(yè) |
| 文件大小： | 677K |
| 代理商： | ISP1362EE,551 |
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ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
57 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating the
bus control lines (MEMR, MEMW, IOR and IOW) and address lines, the CPU
resumes the execution of instructions.
For a typical bulk transfer, the preceding process is repeated 32 times, once for each
word. After each word, the DcAddress register in the DMA controller is incremented by
two and the byte counter is decremented by two. When using the 16-bit DMA, the number
of transfers is 32, and address incrementing and byte counter decrementing is done by
two for each word.
12.4.3 End-Of-Transfer conditions
12.4.3.1
Bulk endpoints
A DMA transfer to or from a bulk endpoint can be terminated by any of the following
conditions (bit names refer to the DcDMAConguration register, see Table 119 and
The DMA transfer completes as programmed in the DcDMACounter register
(CNTREN = 1).
A short packet is received on an enabled OUT endpoint (SHORTP = 1).
DMA operation is disabled by clearing the DMAEN bit.
DcDMACounter register — An EOT from the DcDMACounter register is enabled by
setting bit CNTREN of the DcDMAConguration register. The Peripheral Controller has a
16-bit DcDMACounter register, which species the number of bytes to be transferred.
When DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value
from the DcDMACounter register. When the internal counter completes the transfer as
programmed in the DMA counter, an EOT condition is generated and the DMA operation
stops.
Short packet — Normally, the transfer byte count must be set using a control endpoint
before any DMA transfer takes place. When a short packet has been enabled as EOT
indicator (SHORTP = 1), the transfer size is determined by the presence of a short packet
in data. This mechanism permits the use of a fully autonomous data transfer protocol.
When reading from an OUT endpoint, reception of a short packet at an OUT token will
stop the DMA operation after transferring the data bytes of this packet.
[1]
The DMA transfer stops. No interrupt, however, is generated.
Table 19.
Summary of EOT conditions for a bulk endpoint
EOT condition
OUT endpoint
IN endpoint
DcDMACounter register
transfer completes as
programmed in the
DcDMACounter register
transfer completes as
programmed in the
DcDMACounter register
Short packet
short packet is received and
transferred
counter reaches zero in the
middle of the buffer
DMAEN bit of the
DcDMAConguration register
DMAEN = 0[1]
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| ISP1362EE-S | 功能描述:IC USB CTRL SNGL CHIP 64TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1362EE-T | 功能描述:USB 接口集成電路 USB OTG HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1362EEUM | 功能描述:IC USB OTG CONTROLLER 64-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1362PCI/DOSOTG | 制造商:NXP Semiconductors 功能描述: |
| ISP1501 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Hi-Speed Universal Serial Bus peripheral transceiver |
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