參數(shù)資料
型號： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 145/152頁
文件大?。?/td> 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
92 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
Table 69.
Hc
PInterrupt register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
OTG_IRQ
ATL_IRQ
Reset
------
0
Access
------
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
INTL_IRQ
ClkReady
HC
Suspended
OPR_Reg
AllEOT
Interrupt
ISTL1_
INT
ISTL0_
INT
SOF_INT
Reset
00000000
Access
R/W
Table 70.
Hc
PInterrupt register: bit description
Bit
Symbol
Description
15 to 10
-
reserved
9
OTG_IRQ
0 — no event
1 — The OTG interrupt event must read the OtgInterrupt register to get
the cause of the interrupt.
8
ATL_IRQ
0 — no event
1 — Count value of the HcATLPTDDoneThresholdCount register or the
time-out value of the HcATLPTDDoneThresholdTimeOut register has
reached. The microprocessor is required to read HcATLPTDDoneMap to
check the PTDs that have completed their transactions.
7
INTL_IRQ
0 — no event
1 — The Host Controller has detected the last PTD, and there is at least
one interrupt transaction that has received ACK from the device. The
microprocessor is required to read HcINTLPTDDoneMap to check the
PTDs that have received ACK from the device.
6
ClkReady
0 — no event
1 — The Host Controller has awakened from the ‘suspend’ state, and its
internal clock has turned on again.
5HC
Suspended
0 — no event
1 — The Host Controller has been suspended and no USB activities are
sent from the microprocessor for each ms. The microprocessor can
suspend the Host Controller by setting bits 6 and 7 of the HcControl
register to logic 1. Once the Host Controller is suspended, no SOF needs
to be sent to the devices connected to downstream ports.
4
OPR_Reg
0 — no event
1 — A Host Controller operation has caused a hardware interrupt. It is
necessary for the HCD to read the HcInterruptStatus register to determine
the cause of the interrupt.
3
AllEOT
Interrupt
0 — no event
1 — Data transfer has been completed by using the PIO transfer or the
DMA transfer. This bit is set either when the value of the
HcTransferCounter register has reached zero, or the EOT pin of the Host
Controller is triggered by an external signal.
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