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參數(shù)資料
| 型號： | Intel Celeron Processor |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Mobile Module MMC-2 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動(dòng)模塊和連接器2處理器) |
| 中文描述： | 英特爾賽揚(yáng)處理器的移動(dòng)模塊絲裂霉素在400兆赫，366兆赫，333兆赫和300兆赫2（工作頻率400366333300和266兆赫茲帶移動(dòng)模塊和連接器2處理器） |
| 文件頁數(shù)： | 9/47頁 |
| 文件大小： | 414K |
| 代理商： | INTEL CELERON PROCESSOR |
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Intel
a
Celeron
Processor Mobile Module MMC-2
at 400 MHz, 366 MHz, 333 MHz, and 300 MHz
9
3.1.2
Memory (109 Signals)
Table 2 lists the memory interface signals.
Table 2. Memory Signal Descriptions
Name
Type
Voltage
Description
MECC[7:0]
I/O
CMOS
V_3
Memory ECC Data:
These signals carry Memory ECC data during access to DRAM.
ECC is not supported on the Celeron processor mobile module.
RASA[5:0]# or
CSA[5:0]#
O
CMOS
V_3
Row Address Strobe (EDO):
These pins select the DRAM row.
Chip Select (SDRAM):
These pins activate the SDRAMs.
SDRAM accepts any
command when its CS# pin is active low.
CASA[7:0]# or
DQMA[7:0]
O
CMOS
V_3
Column Address Strobe (EDO):
These pins select the DRAM column.
Input/Output Data Mask (SDRAM):
These pins act as synchronized output enables
during a read cycle and as a byte mask during a write cycle.
MAB[9:0]#
MAB[10]
MAB[12:11]#
MAB[13]
O
CMOS
V_3
Memory Address (EDO/SDRAM):
This is the row and column address for DRAM.
The
82433BX Host Bridge system controller has two identical sets of address lines (MAA
and MAB#). The module supports only the MAB set of address lines. For additional
addressing features, please refer to the
Intel
a
440BX AGPset Datasheet.
MWEA#
O
CMOS
O
CMOS
V_3
Memory Write Enable (EDO/SDRAM):
MWEA# should be used as the write enable for
the memory data bus.
SRASA#
V_3
SDRAM Row Address Strobe (SDRAM):
When active low, this signal latches Row
Address on the positive edge of the clock. This signal also allows Row access and pre-
charge.
SCASA#
O
CMOS
V_3
SDRAM Column Address Strobe (SDRAM):
When active low, this signal latches
Column Address on the positive edge of the clock.
This signal also allows Column
access.
CKE[5:0]
O
CMOS
V_3
SDRAM Clock Enable (SDRAM):
SDRAM clock enable pin. When these signals are
deasserted, SDRAM enters power-down mode.
Each row is individually controlled by its
own clock enable.
MD[63:0]
I/O
CMOS
V_3
Memory Data:
These signals are connected to the DRAM data bus. They are not
terminated on the Celeron processor mobile module MMC-2.
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