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參數資料
| 型號： | Intel Celeron Processor |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Mobile Module MMC-2 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動模塊和連接器2處理器) |
| 中文描述： | 英特爾賽揚處理器的移動模塊絲裂霉素在400兆赫，366兆赫，333兆赫和300兆赫2（工作頻率400366333300和266兆赫茲帶移動模塊和連接器2處理器） |
| 文件頁數： | 22/47頁 |
| 文件大?。?/td> | 414K |
| 代理商： | INTEL CELERON PROCESSOR |
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Intel
a
Celeron
Processor Mobile Module MMC-2
at 400 MHz, 366 MHz, 333 MHz, and 300 MHz
22
Table 13 summarizes some of the key specifications for the connector.
Table 13. Connector Specifications
Condition
Parameter
Specification
Material
Contact
Copper Alloy
Housing
Thermo Plastic Molded Compound: LCP
Electrical
Current
0.5A
Voltage
50 VAC
Insulation Resistance
100 M
minimum at 500 VDC
Termination Resistance
10 m
maximum
Capacitance
5 pF maximum per contact
Mechanical
Mating Cycles
50 cycles
Connector Mating Force
2.0 oz maximum per contact
Contact Unmating Force
1.5 oz minimum per contact
4.0
FUNCTIONAL DESCRIPTION
4.1
Celeron Processor Mobile Module MMC-2
The Celeron processor mobile module MMC-2 offers core
speeds of 400 megahertz, 366 megahertz, 333 megahertz,
and 300 megahertz. All processor speeds have a 66-
megahertz PSB speed.
4.2
L2 Cache
The on-die L2 cache is 128 kilobytes, is four-way set
associative, and runs at the speed of the processor core.
4.3
The 82433BX Host Bridge System
Controller
Intel’s 82433BX Host Bridge system controller is a highly
integrated device that combines the bus controller, the
DRAM controller, and the PCI bus controller into one
component. The 82433BX Host Bridge has multiple power
management features designed specifically for notebook
systems such as:
CLKRUN#, a feature that enables controlling of the PCI
clock on or off.
The 82433BX Host Bridge suspend modes, which
include Suspend-to-RAM (STR), Suspend-to-Disk
(STD), and Power-On-Suspend (POS).
System Management RAM (SMRAM) power
management modes, which include Compatible
SMRAM (C_SMRAM) and Extended SMRAM
(E_SMRAM). C_SMRAM is the traditional SMRAM
feature implemented in all Intel PCI chipsets.
E_SMRAM is a new feature that supports write-back
cacheable SMRAM space up to 1 megabyte. To
minimize power consumption while the system is idle,
the internal 82433BX Host Bridge clock is turned off
(gated off) when there is no processor and PCI activity.
This is accomplished by setting the G_CLK enable bit in
the power management register in the 82433BX
through the system BIOS.
4.3.1
Memory Organization
The memory interface of the 82433BX Host Bridge is
available at connector. This allows for the following:
One set of memory control signals, sufficient to support
up to three SO-DIMM sockets and six banks of SDRAM
at 66 megahertz.
One CKE signal for each bank.
Memory features not supported by the 82433BX Host Bridge
system controller standard MMC-2 mode are:
Support for eight banks of memory.
Second set of memory address lines (MAA[13:0]).
DRAM technologies supported by the 82433BX Host Bridge
system controller include EDO and SDRAM. These memory
types may not be mixed in the system, so that all DRAM in
all rows (RAS[5:0]#) must be of the same technology. The
82433BX Host Bridge system controller targets 60
nanoseconds EDO DRAMs and 66-megahertz SDRAMs.
The Celeron processor mobile module MMC-2’s clocking
architecture supports the use of SDRAM. Tight timing
requirements of the 66-megahertz SDRAM clocks allow all
host and SDRAM clocks to be generated from the same
clocking architecture. For complete details about using
SDRAM memory and for trace length guidelines, refer to the
Mobile Pentium II processor / 82433BX AGPset Advanced
Platform Recommended Design and Debug Practices.
Refer
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