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參數(shù)資料
| 型號： | Intel Celeron Processor |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Mobile Module MMC-2 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動(dòng)模塊和連接器2處理器) |
| 中文描述： | 英特爾賽揚(yáng)處理器的移動(dòng)模塊絲裂霉素在400兆赫，366兆赫，333兆赫和300兆赫2（工作頻率400366333300和266兆赫茲帶移動(dòng)模塊和連接器2處理器） |
| 文件頁數(shù)： | 24/47頁 |
| 文件大?。?/td> | 414K |
| 代理商： | INTEL CELERON PROCESSOR |
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Intel
a
Celeron
Processor Mobile Module MMC-2
at 400 MHz, 366 MHz, 333 MHz, and 300 MHz
24
clock state are mutually exclusive. For example, a strapping
option on signal A15# chooses which state is entered when
the STPCLK# signal is asserted. Strapping the A15# signal
enables the Quick Start state to ground at Reset. Otherwise,
asserting the STPCLK# signal puts the processor into the
Stop Grant state. The Stop Grant state is useful for SMP
platforms and is not supported on the Celeron processor
mobile module. The Quick Start state is available on the
module and provides a significantly lower power level.
Figure 3 provides an illustration of the clock control
architecture. State transitions not shown in Figure 3 are
neither recommended nor supported
HALT/Grant
Snoop
Normal
State
HS=false
Stop
Grant
Auto
Halt
HS=true
Quick
Start
Sleep
Deep
Sleep
(!STPCLK#
and !HS) or
stop break
STPCLK# and
!QSE and SGA
Snoop
occurs
Snoop
serviced
STPCLK# and
QSE and SGA
(!STPCLK# and !HS)
or RESET#
Snoop
serviced
Snoop
occurs
!STPCLK#
and HS
STPCLK# and
!QSE and SGA
HLT and
halt bus cycle
halt
break
Snoop
serviced
Snoop
occurs
STPCLK# and
QSE and SGA
!STPCLK#
and HS
!SLP# or
RESET#
SLP#
BCLK
stopped
BCLK on
and !QSE
BCLK
stopped
BCLK on
and QSE
Halt break – A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#
HLT – HLT instruction executed
HS – Processor Halt State
QSE – Quick Start State Enabled
SGA – Stop Grant Acknowledge bus cycle issued
Stop break – BINIT#, FLUSH#, RESET#
Intel Mobile Modules do not support the shaded clock states
Figure 3. Clock Control States
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