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參數(shù)資料
| 型號： | Intel Celeron Processor |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Mobile Module MMC-2 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動模塊和連接器2處理器) |
| 中文描述： | 英特爾賽揚處理器的移動模塊絲裂霉素在400兆赫，366兆赫，333兆赫和300兆赫2（工作頻率400366333300和266兆赫茲帶移動模塊和連接器2處理器） |
| 文件頁數(shù)： | 13/47頁 |
| 文件大?。?/td> | 414K |
| 代理商： | INTEL CELERON PROCESSOR |
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Intel
a
Celeron
Processor Mobile Module MMC-2
at 400 MHz, 366 MHz, 333 MHz, and 300 MHz
13
3.1.6
Processor/PIIX4E/M Sideband (8 Signals)
Table 6 lists the signals for the processor and the PIIX4E/M
sideband signals. The voltage level for these signals is
determined by V_CPUPU.
Table 6. Processor/PIIX4E/M Sideband Signal Descriptions
Voltage
Name
Type
Description
FERR#
O
CMOS
V_CPUPU
Numeric Coprocessor Error:
This pin functions as a FERR# signal supporting
coprocessor errors. This signal is tied to the coprocessor error signal on the processor
and is driven by the processor to the PIIX4E/M
IGNNE#
I D
CMOS
I D
CMOS
I D
CMOS
I D
CMOS
V_CPUPU
Ignore Error:
This open-drain signal is connected to the Ignore Error pin on the
processor and is driven by the PIIX4E/M.
INIT#
V_CPUPU
Initialization:
INIT# is asserted by the PIIX4E/Mto the processor for system
initialization. This signal is an open-drain.
INTR
V_CPUPU
Processor Interrupt:
INTR is driven by the PIIX4E/Mto signal the processor that an
interrupt request is pending and needs to be serviced. This signal is an open-drain.
NMI
V_CPUPU
Non-maskable Interrupt:
NMI is used to force a non-maskable interrupt to the
processor.
The PIIX4E/M ISA bridge generates a NMI when either SERR# or IOCHK# is
asserted, depending on how the NMI Status and Control Register is programmed. This
signal is an open-drain.
A20M#
I D
CMOS
I D
CMOS
V_CPUPU
Address Bit 20 Mask:
When enabled, this open-drain signal causes the processor to
emulate the address wraparound at one MB, which occurs on the Intel 8086 processor.
SMI#
V_CPUPU
System Management Interrupt:
SMI# is an active low synchronous output from the
PIIX4E/M that is asserted in response to one of many enabled hardware or software
events.
The SMI# open-drain signal can be an asynchronous input to the processor.
However, in this chip set SMI# is synchronous to PCLK.
STPCLK#
I D
CMOS
V_CPUPU
Stop Clock:
STPCLK# is an active low synchronous open-drain output from the
PIIX4E/M that is asserted in response to one of many hardware or software events.
STPCLK# connects directly to the processor and is synchronous to PCICLK.
When the
processor samples STPCLK# asserted, it responds by entering a low power state (Quick
Start). The processor will only exit this mode when this signal is deasserted.
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