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參數(shù)資料
| 型號： | Intel Celeron Processor |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Mobile Module MMC-2 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動模塊和連接器2處理器) |
| 中文描述： | 英特爾賽揚(yáng)處理器的移動模塊絲裂霉素在400兆赫，366兆赫，333兆赫和300兆赫2（工作頻率400366333300和266兆赫茲帶移動模塊和連接器2處理器） |
| 文件頁數(shù)： | 28/47頁 |
| 文件大?。?/td> | 414K |
| 代理商： | INTEL CELERON PROCESSOR |
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Intel
a
Celeron
Processor Mobile Module MMC-2
at 400 MHz, 366 MHz, 333 MHz, and 300 MHz
28
4.6.2
AC Requirements
Table 18 shows the BCLK AC requirements.
Table 18. AC Specifications at the Processor Core Pins
1,2,3
Min
Nom
T#
PSB Frequency
4
Parameter
Max
Unit
Figure
Notes
66.67
MHz
All processor core
frequencies
T1:
BCLK Period
4, 5
BCLK Period Stability
6, 7, 8
15.0
ns
T2:
±250
ps
T3:
BCLK High Time
5.3
ns
At >1.8V
T4:
BCLK Low Time
BCLK Rise Time
8
BCLK Fall Time
8
5.3
ns
At <0.7V
T5:
0.175
0.875
ns
(0.9V-1.6V)
T6:
0.175
0.875
ns
(1.6V–0.9V)
NOTES:
1.
2.
Unless otherwise noted, all specifications in this table apply to all Intel mobile modules.
All AC timings for the GTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor core pin. All GTL+ signal
timings (address bus, data bus, etc.) are referenced at 1.00V at the processor core pins.
All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25V at the processor core pin. All CMOS signal
timings (compatibility signals, etc.) are referenced at 1.25V at the processor core pins.
The internal core clock frequency is derived from the PSB clock. The PSB clock to core clock ratio is determined during initialization
as described and is predetermined by the Celeron processor mobile module MMC-2.
The BCLK period allows a +0.5 ns tolerance for clock driver variation. See the
CK97 Clock Synthesizer/Driver Specification
for further
information.
Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a component of BCLK skew
between devices.
The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the jitter created by the clock
driver. The -20 dB attenuation point, as measured into a 10-pF to a 20-pF load, should be less than 500 kHz. This specification may
be ensured by design characterization and/or measured with a spectrum analyzer. See the
CK97 Clock Synthesizer/Driver
Specification
for further details.
Not 100% tested. Specified by design characterization as a clock driver requirement.
3.
4.
5.
6.
7.
8.
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