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參數(shù)資料
| 型號(hào)： | Intel Celeron Processor |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Mobile Module MMC-2 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動(dòng)模塊和連接器2處理器) |
| 中文描述： | 英特爾賽揚(yáng)處理器的移動(dòng)模塊絲裂霉素在400兆赫，366兆赫，333兆赫和300兆赫2（工作頻率400366333300和266兆赫茲帶移動(dòng)模塊和連接器2處理器） |
| 文件頁數(shù)： | 16/47頁 |
| 文件大小： | 414K |
| 代理商： | INTEL CELERON PROCESSOR |
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Intel
a
Celeron
Processor Mobile Module MMC-2
at 400 MHz, 366 MHz, 333 MHz, and 300 MHz
16
3.1.9
Voltages (54 Signals)
Table 9 lists the voltage signal definitions.
Table 9. Voltage Descriptions
Name
Type
Number
of Pins
20
Description
V_DC
I
DC Input:
5V-21V
V_3S
I
9
SUSB# controlled 3.3V:
This rail is not used on the module.
However, it is a power
managed 3.3-V supply.
An output of the voltage regulator on the system electronics.
This rail is off during STR, STD, and Soff.
V_5
I
3
SUSC# controlled 5V:
Power managed 5.0-V supply.
An output of the voltage regulator
on the system electronics. This rail is off during STD and Soff.
V_3
I
16
SUSC# controlled 3.3V:
Power managed 3.3-V supply.
An output of the voltage
regulator on the system electronics. This rail is off during STD and Soff.
VCCAGP
I
4
AGP I/O Voltage
: This voltage rail is not implemented on module and is defined for
upgrade purposes only. Intel recommends that this voltage rail be connected to V_3 on
the system electronics.
V_CPUPU
O
1
Processor I/O Ring:
Driven by the module to power processor interface signals such as
the PIIX4E/M open-drain pullups for the processor/PIIX4E/Msideband signals.
V_CLK
O
1
Processor Clock Rail:
Driven by the module to power CK100-M VDDCPU rail.
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