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參數(shù)資料
| 型號： | Intel Celeron Processor |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Mobile Module MMC-2 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動模塊和連接器2處理器) |
| 中文描述： | 英特爾賽揚處理器的移動模塊絲裂霉素在400兆赫，366兆赫，333兆赫和300兆赫2（工作頻率400366333300和266兆赫茲帶移動模塊和連接器2處理器） |
| 文件頁數(shù)： | 17/47頁 |
| 文件大?。?/td> | 414K |
| 代理商： | INTEL CELERON PROCESSOR |
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Intel
a
Celeron
Processor Mobile Module MMC-2
at 400 MHz, 366 MHz, 333 MHz, and 300 MHz
17
3.1.10
ITP/JTAG (9 Signals)
Table 10 lists the ITP/JTAG signals, which the system
manufacturer can use to implement a JTAG chain and an
ITP port if desired.
Table 10. ITP/JTAG Pins
Name
Type
Voltage
Description
TDO
O
V_CPUPU
JTAG Test Data Out:
Serial output port. TAP instructions and data are shifted out of the
processor from this port.
TDI
I
V_CPUPU
JTAG Test Data In:
Serial input port. TAP instructions and data are shifted into the
processor from this port.
TMS
I
V_CPUPU
JTAG Test Mode Select:
Controls the TAP controller change sequence.
TCLK
I
V_CPUPU
JTAG Test Clock:
Testability clock for clocking the JTAG boundary scan sequence.
TRST#
I
V_CPUPU
JTAG Test Reset:
Asynchronously resets the TAP controller in the processor.
FS_RESET#
O
GTL+
Processor Reset:
Processor reset status to the ITP.
VTT
O
V_CORE
GTL+ Termination Voltage:
Used by the POWERON pin on the ITP debug port to
determine when target system is on. POWERON pin is pulled up using a 1-K
resistor
to VTT.
FS_PREQ#
I
V_CPUPU
Debug Mode Request:
Driven by the ITP and makes request to enter debug mode.
FS_PRDY#
O
GTL+
Debug Mode Ready:
Driven by the processor and informs the ITP that the processor is
in debug mode.
NOTE:
DBREST# (reset target system) on the ITP debug port can be “l(fā)ogically ANDed” with VR_PWRGD TO PIIX4E/M’s PWROK.
3.1.11
Miscellaneous (82 Signals)
Table 11 lists the miscellaneous signal pins.
Table 11. Miscellaneous Pins
Name
Type
Number
Description
Module
ID[3:0]
O
CMOS
4
Module Revision ID
: These pins track the revision level of the Celeron processor
mobile module MMC-2. A 100-K pullup resistor to V_3S must be placed on the system
electronics for these signals. See Section 7.0, “Labeling Information” for more
information.
Ground
I
45
Ground.
Reserved
RSVD
33
Unallocated Reserved pins and should not be connected.
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