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參數(shù)資料
| 型號： | Intel Celeron Processor |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Mobile Module MMC-2 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動模塊和連接器2處理器) |
| 中文描述： | 英特爾賽揚(yáng)處理器的移動模塊絲裂霉素在400兆赫，366兆赫，333兆赫和300兆赫2（工作頻率400366333300和266兆赫茲帶移動模塊和連接器2處理器） |
| 文件頁數(shù)： | 26/47頁 |
| 文件大小： | 414K |
| 代理商： | INTEL CELERON PROCESSOR |
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Intel
a
Celeron
Processor Mobile Module MMC-2
at 400 MHz, 366 MHz, 333 MHz, and 300 MHz
26
Grant state the SLP# signal can be asserted, causing the
processor to enter the Sleep state. The SLP# signal is not
recognized in the Normal state or the Auto Halt state.
The processor can be reset by the RESET# signal while in
the Sleep state. If RESET# is driven active while the
processor is in the Sleep state, then SLP# and STPCLK#
must immediately be driven inactive to ensure that the
processor correctly initializes itself.
Input signals (other than RESET#) may not change while the
processor is in the Sleep state or transitioning into or out of
the Sleep state. Input signal changes at these times will
cause unpredictable behavior. Thus, the processor is
incapable of snooping or latching any events in the Sleep
state.
While in the Sleep state the processor can enter its lowest
power state, the Deep Sleep state. Removing the
processor’s input clock puts the processor in the Deep Sleep
state. PICCLK may be removed in the Sleep state.
4.4.8
Deep Sleep State
The Deep Sleep state is the lowest power mode the
processor can enter while maintaining its context. Stopping
the BCLK input to the processor enters the Deep Sleep
state, while it is in the Sleep state or the Quick Start state.
For proper operation, the BCLK input should be stopped in
the low state.
The processor will return to the Sleep state or the Quick
Start state from the Deep Sleep state when the BCLK input
is restarted. Due to the PLL lock latency, there is a 30-
millisecond delay after the clocks have started before this
state transition happens. PICCLK may be removed in the
Deep Sleep state. PICCLK should be designed to turn on
when BCLK turns on when transitioning out of the Deep
Sleep state.
The input signal restrictions for the Deep Sleep state are the
same as for the Sleep state, except that RESET# assertion
will result in unpredictable behavior.
Table 15. Clock State Characteristics
Processor
Power
Clock
State
Exit Latency
Snooping
System Uses
Normal
N/A
Varies
Yes
Normal program execution.
Auto Halt
Approximately 10 bus clocks
1.2W
Yes
S/W controlled entry idle mode.
Stop Grant
1
10 bus clocks
1.2W
Yes
H/W controlled entry/exit mobile throttling.
Quick Start
Through snoop, to HALT/Grant
Snoop state: immediate
Through STPCLK#, to Normal
state: 10 bus clocks
0.5W
Yes
H/W controlled entry/exit mobile throttling.
HALT/Grant
Snoop
A few bus clocks after the end of
snoop activity.
Not
specified
Yes
Supports snooping in the low power states.
Sleep
1
To Stop Grant state 10 bus clocks
0.5W
No
H/W controlled entry/exit desktop idle mode
support.
Deep Sleep
30 ms
150 mW
No
H/W controlled entry/exit mobile powered-on
suspend support.
NOTES:
1.
2.
Intel mobile modules do not support shaded clock control states.
Not 100% tested. Specified at 50
°
C by design and characterization.
4.5
Typical POS and STR Power
Table 16 shows the typical POS and STR power values.
Table 16. POS and STR Power
State
Typical MMC-2 Power
POS
0.475W
STR
0.018W
NOTE
:
These are average values of measurement and are guidelines only.
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