參數(shù)資料
型號： IBM3209K3114
廠商： IBM Microeletronics
英文描述： IBM Packet Routing Switch Serial Interface Converter(IBM封裝路線選擇開關串行接口轉(zhuǎn)換器)
中文描述： IBM的分組路由交換機串行接口轉(zhuǎn)換器（IBM的封裝路線選擇開關串行接口轉(zhuǎn)換器）
文件頁數(shù)： 9/152頁
文件大?。?/td> 2390K
代理商： IBM3209K3114
IBM3209K3114
IBM Packet Routing Switch Serial Interface Converter
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Page vii
prssi.01LOT.fm
July 10, 2000
List of Tables
Table 1: Ingress I/O Pin Description ............................................................................................... 9
Table 2: Egress I/O Pin Description .............................................................................................. 13
Table 3: Output Port Bitmap Fields ............................................................................................... 17
Table 4: Packet Qualifier for Ingress Idle Packet .......................................................................... 18
Table 5: Packet Qualifier for Ingress Data Packet ........................................................................ 18
Table 6: Packet Qualifier for Ingress Data Packet ........................................................................ 19
Table 7: Packet Qualifier for Egress Idle Packet .......................................................................... 20
Table 8: Packet Qualifier for Egress Data Packet ........................................................................ 21
Table 9: Packet Qualifier for Egress Data Packet ........................................................................ 22
Table 10: Output Queue Grant Bit Map Fields ............................................................................. 29
Table 11: Selecting the Signal That Appears on the TO_SMOOTH_PLL_IN Signal .................... 34
Table 12: External Clocks Description .......................................................................................... 35
Table 13: Register Reset Settings ................................................................................................ 36
Table 14: I/O Initialization Values ................................................................................................. 37
Table 15: Path Resets .................................................................................................................. 37
Table 16: System Mode PLL Resets ............................................................................................ 38
Table 17: Supported JTAG Instructions ........................................................................................ 97
Table 18: Compliance Pattern ...................................................................................................... 98
Table 19: ID Code Description ...................................................................................................... 98
Table 20: Tests Signals ................................................................................................................ 99
Table 21: JTAG Interface External Signals ................................................................................. 100
Table 22: Processor Interface Signals ........................................................................................ 101
Table 23: IBM Packet Routing Switch Serial Interface Converter (the converter) Signals ......... 102
Table 24: Receive PE Interface Signals ..................................................................................... 103
Table 25: Transmit PE Interface Signals .................................................................................... 103
Table 26: Clocking/PLL External Signals .................................................................................... 104
Table 27: Back Pressure Serial Link Signals .............................................................................. 105
Table 28: Miscellaneous External Signals .................................................................................. 106
Table 29: Spares Signals Used to Carry Additional DC Voltages .............................................. 107
Table 30: Debug Purpose External Signals ................................................................................ 107
Table 31: DBG_SELECT Bus Definition ..................................................................................... 108
Table 32: Absolute Maximum Ratings ........................................................................................ 114
Table 33: LVCMOS Compatible I/Os .......................................................................................... 115
Table 34: LVTTL Compatible I/Os .............................................................................................. 115
Table 35: Recommended Operating Conditions for all I/Os ....................................................... 116
Table 36: Power Dissipation ....................................................................................................... 116
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