參數(shù)資料
型號(hào)： IBM3209K3114
廠商： IBM Microeletronics
英文描述： IBM Packet Routing Switch Serial Interface Converter(IBM封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器)
中文描述： IBM的分組路由交換機(jī)串行接口轉(zhuǎn)換器（IBM的封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器）
文件頁數(shù)： 47/152頁
文件大?。?/td> 2390K
代理商： IBM3209K3114
IBM3209K3114
Advance
IBM Packet Routing Switch Serial Interface Converter
prssi.01
July 12, 2000
Functional Description
Page 37 of 142
After POR action, the converter must be re-configured via the μP_interface. The PLLs are switched into
BYPASS mode and neither PATH X nor PATH Y are configured.
POR external signal is an asynchronous signal. POR initiates when the POR signal input is going down. POR
procedure stops when the POR signal input is held up. POR must be asserted for at least 10 MP_CLK cycles
to insure proper chip reset.
The following table shows pin/pad TEST I/O initialization values (the values during and after reset):
3.9.3 Path Reset
Individual PATH X and PATH Y resets are performed by addressing an appropriated bit in the
COMMON_CONFIG_REGISTER @A0 (CCR). SWITCH_X_PLL or SWITCH_Y_PLL must run during the
PATH X/Y reset action. PLLs are not affected by PATH X/Y resets, but the PLL must be reset when an
external loopback is initiated with a new clock source (PLL needs a delay to lock). Once a reset is estab-
lished, the software must reconfigure the CCR @A0 bits 0, 1, 2, 3
into the system mode.
Table 14: I/O Initialization Values
Pin Name
Value in System
Description
CE1_A
1
LSSD test A clock
CE1_B
1
LSSD test B clock
CE1_C1
1
LSSD test C clock
CE1_C2
1
LSSD test C clock
CE0_IO
0
Used to force the JTAG EXTEST operation
CEO_Scan
0
A and B clock gating, used also to Clock Splitter GATE input
CE0_TEST
0
Used to control Boundary Scan feature
TEST_B2
1
LSSD test B clock (if required)
TEST_C3
1
LSSD test C clock (if required)
DI1
1
Driver Inhibit (for non test I/O)
DI2
1
Driver Inhibit (for test I/O)
RI
1
Receiver Inhibit
TDI
1
JTAG serial input
TCK
1
JTAG clock
TMS
1
JTAG control signal
TRST
1
JTAG asynchronous reset
Table 15: Path Resets
Reset Name
Impact
Reset
PATH X
No impact on PATH Y
Program CCR @A0 bit 0 at
‘
1
’
in the configuration table registers.
PATH Y
no impact on PATH X
Program CCR @A0 bit 1 at
‘
1
’
in the configuration table registers.
DASL_X
no impact on DASL_Y
Program CCR @A0 bit 2 at
‘
1
’
in the configuration table registers.
DASL_Y
no impact on DASL_X
Program CCR @A0 bit 3 at
‘
1
’
in the configuration table registers.
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