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參數(shù)資料
| 型號(hào)： | IBM3209K3114 |
| 廠商： | IBM Microeletronics |
| 英文描述： | IBM Packet Routing Switch Serial Interface Converter(IBM封裝路線選擇開(kāi)關(guān)串行接口轉(zhuǎn)換器) |
| 中文描述： | IBM的分組路由交換機(jī)串行接口轉(zhuǎn)換器（IBM的封裝路線選擇開(kāi)關(guān)串行接口轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 114/152頁(yè) |
| 文件大?。?/td> | 2390K |
| 代理商： | IBM3209K3114 |
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IBM3209K3114
IBM Packet Routing Switch Serial Interface Converter
Advance
I/O Definition and Package Pin Assignment
Page 104 of 142
prssi.01
July 12, 2000
To provide isolation from the noisy internal digital V
dd
signal, VDDA is brought to a package pin. If little noise
is expected at the board level, then VDDA can be connected directly to the digital V
dd
plane. In most circum-
stances, it is prudent to palce a filter circuit on VDDA as shown below. All wire lengths should be kept as short
as possible to minimize coupling from other signals. The impedance of the ferrite bead should be much
greater than that of the capacitor at frequencies where noise is expected. Many applications have found that
a resistor, instead of a ferrite bead, does a better job of reducing jitter. The resistor should be kept to a value
lowr than 2
.
Experimentation is the best way to determine the optimal fileter design for a specific applica-
tion.
Table 26: Clocking/PLL External Signals
Name
Input/
Output
Levels
Description
+SWITCH_X_CLK / -
SWITCH_X_CLK
Input
HSTL (balanced)
Switch Core X system clock used for the internal clock generation in
the switch X interface side (clock frequency is 55 - 62.5 MHz).
+SWITCH_Y_CLK / -
SWITCH_Y_CLK
Input
HSTL (balanced)
Switch Core Y system clock used for the internal clock generation in
the switch Y interface side (clock frequency is 55 - 62.5 MHz).
MP_CLK
Inputs
LVTTL
Processor Bus clock input: 25 - 66 MHz. This clock also drives the PE
interface when no other clock has been selected by setting register
@A0 bit 30-31 to b
’
00
’
or
’
11
’
(default settings)
PE_CLK
Input
LVCMOS
Clock used to drive all converter PE side actions. Clock source can
drive the PE interface by setting register @A0 bit 31-30 to b
’
01
’
FROM_SMOOTH_
PLL_OUT
Input
LVTTL
Clock derived from the in service clock and smoothed by an external
PLL in case of clock switch-over. Used to drive all PE side actions of
the converter. Clock source can drive the PE interface by setting regis-
ter @A0 bit 31-30 to b
’
10
’
TO_SMOOTH_PLL_
IN
Output
LVTTL
Raw clock derived from the in service clock source of either switch fab-
ric derived from either the switch X or the switch Y clock source
depending on the status of the Switch X or Y InService lines from the
switch core. It can be forced to be either switch X or Y clock according
to the plane which has been forced in the configuration register @A4
bits 21 and 22. Enable bit 26 at configuration @A4 enables this signal
PE_TXCLK_OUT
Ouput
LVCMOS
Clock delivered by the converter that allows the transfer/synchroniza-
tion of the TXDATA[31:0] and their associated controls from the con-
verter to the PE. Clock source is determined by configuration register
@A0 bit 31-30. Enabling this clock
’
s driver depends on register @C0
bit 8.
PE_RXCLK_out
Output
LVCMOS
Clock delivered by the converter in case PE_CLK is not available on
the PE layer. Allows the transfer/synchronization of the RXDATA[31:0]
and their associated controls from the PE to the DASL chip. Clock
source is determined by configuration register @A0 bit 31-30. Enabling
this clock
’
s driver depends on register @C0 bit 10
SHADOW_RXCLK_
OUT
Output
LVCMOS
Clock delivered by the converter to allow a matched sampling with the
Receive data coming from the PE. It can be connected to either an on
board delay line or the attached PE to provide (along with
SHADOW_RXCLOCK_IN) a clock phase incurring the same delay as
the data. Enabling this clock
’
s driver depends on register @C0 bit 10.
SHADOW_RXCLK_I
N
Input
LVCMOS
Clock derived from the SHADOW_RXCLK_OUT after having passed
through either an onboard delay line or the PE. It can be used to sam-
ple the ingress receive data.
SWITCH_X_VDDA
Input
PLL Analog VDD
Required to get a dedicated filtered voltage to switch X the PLL
SWITCH_Y_VDDA
Input
PLL Analog VDD
Required to get a dedicated filtered voltage to switch Y the PLL
PE_VDDA
Input
PLL Analog VDD
Required to get a dedicated filtered voltage to PE the PLL.
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