參數(shù)資料
型號: IBM3209K3114
廠商: IBM Microeletronics
英文描述: IBM Packet Routing Switch Serial Interface Converter(IBM封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器)
中文描述: IBM的分組路由交換機串行接口轉(zhuǎn)換器(IBM的封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器)
文件頁數(shù): 24/152頁
文件大小: 2390K
代理商: IBM3209K3114
IBM3209K3114
IBM Packet Routing Switch Serial Interface Converter
Advance
Functional Description
Page 14 of 142
prssi.01
July 12, 2000
3.2.2.2 Egress Operation and Timing
3.2.3 TXFULL Timing
When the PE asserts TXFULL to stop the flow of packets, its effect is extended for 28 PE clock cycles from
the end of the current packet. After the first packet following the deassertion of TXFULL by the PE, the
UDASL inserts two empty slots of idle (no data) before the traffic resumes. If the PE resasserts TXFULL upon
the reception of the first packet during the TXFULL cycle, it will be ignored until the end of the complete cycle.
Figure 10: TXFULL Timing
Figure 11: Egress Timing for Back-to-Back Packets
Transmit Operation for 64-Byte Back-t0-Back Packet Transmission
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
DATA PKT
DATA PKT
DATA PKT
DATA PKT
1 PKT
~
1 PKT
~
DATA PKT
DATA PKT
DATA PKT
DATA PKT
DATA PKT
DATA PKT
1 PKT
~
1 PKT
~
DATA PKT
DATA PKT
Ignored
CLK
TXDATA[31:0]
TXFULL
TXDATA[31:0]
TXFULL Cycle
28 CLK CYCLES
28 CLK CYCLES
TXFULL Cycle
T0
T2
T4
T6
T8
T10
T12
T14
T16
T18
T20
T22
T24
NOP NOPNOP H1
H2
W1 W2
W3
W4
W5
W6
W7
W8
W9 W10 W11 W12 W13 W14
H1
H2
W1
W2
W4
Protocol engine ready
to accept a new packet
W3
Converter keeps
TXENB asserted
1
2
3
4
PE_TXCLK_OUT
TXDATA[31:0]
TXSOP
TXPAV
TXENB
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