參數(shù)資料
型號(hào)： IBM3209K3114
廠商： IBM Microeletronics
英文描述： IBM Packet Routing Switch Serial Interface Converter(IBM封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器)
中文描述： IBM的分組路由交換機(jī)串行接口轉(zhuǎn)換器（IBM的封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器）
文件頁數(shù)： 33/152頁
文件大?。?/td> 2390K
代理商： IBM3209K3114
IBM3209K3114
Advance
IBM Packet Routing Switch Serial Interface Converter
prssi.01
July 12, 2000
Functional Description
Page 23 of 142
3.4 Packet Buffering
3.4.1 X and Y Path Receive FIFO (RXFIFO)
The RXFIFO block:
Writes the data coming from the ingress formatter (clocked on the PE clock (URXCLK)) to the FIFO
Reads the data from FIFO to the X and Y paths to the ingress DASL interface (IDI) block, clocked on the
X/Y path clock (accounting for the size of the packet in steps of four bytes)
Detects and reports a FIFO almost full event, whose threshold is programmable through configuration
registers
Depending upon the configuration table, it either de-asserts RXENB (if it is in use), or de-grants Shared
Memory priority 0 (highest) to create room in the RXFIFO when there is an indication of FIFO almost full.
The FIFO is 256 bytes wide, or three 80-bytes packets. A 3-packet buffer temporarily stores incoming data
packets, thereby allowing the insertion of a yellow packet without requiring any link level flow control. This
absorbs any clock difference between the PE and the switch
3.4.2 X/Y Path Transmit FIFO (TXFIFO)
The X and Y path TXFIFO block:
Writes the data coming from the X or Y path TX EXTRACTION BLOCK, as clocked on DASL_X_CLK or
DASL_Y_CLK respectively, to the FIFO
Reads the data from the FIFO to the path selection block, clocked on UTXCLK (PE clock)
Detects and reports a FIFO almost full event, whose threshold is programmable
Detects and reports a FIFO not empty, whose threshold is programmable
Stops its data flow when the path selection block decides
Data packets are never written in the unused path
’
s FIFO.
When the FIFO is almost full, send grant to the switch is de-asserted.
The FIFO is 480 bytes wide, i.e. six 80-bytes packets. Six packets of buffer in the TX FIFO take into account
the switch
’
or de-asserting send grant.
3.5 Path Selection Block
This block selects the X or Y FIFO depending on the switch control
’
s X_inService or Y_inService inputs
.
Only
the selected path
’
s TXFIFO is filled with packets, the other one is empty. Switching from one plane to the
other is done on a packet boundary. However, there can be duplicated or missing packets.
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