
IBM3209K3114
IBM Packet Routing Switch Serial Interface Converter
Advance
Page iii
prssi.01TOC.fm
July 10, 2000
4.1.1.19 SDC Address X Bus Register (SDC_Debug_Data_Address X) ................................... 69
4.1.1.20 SDC Status X Register (SDC_Status_Reg X) .............................................................. 70
4.1.1.21 DASL M3 Picocode Y Register ..................................................................................... 71
4.1.1.22 SDC Controller Y Register (SDC_Debug_CNTL Y) ..................................................... 72
4.1.1.23 SDC Y Data In Bus Register (SDC_Debug_Data_In Y) ............................................... 73
4.1.1.24 SDC Data Y Out Bus Register (SDC_Data Y_Out Bus) ............................................... 74
4.1.1.25 SDC Address Y Bus Register (SDC_Debug_Data_Address Y) ................................... 75
4.1.1.26 SDC Status Y Register (SDC_Status_Reg Y) .............................................................. 76
4.1.1.27 Event 2 Checker Enable_X and _Y Registers .............................................................. 77
4.1.1.28 Event 2 μP Interrupt Enable_X and _Y Registers ........................................................ 78
4.1.1.29 Event 2 _X and _Y Registers ....................................................................................... 79
4.1.1.30 ABIST Failure Test Status _X_Y Registers .................................................................. 81
4.1.1.31 Switch X PLL Setting Register ...................................................................................... 82
4.1.1.32 Switch Y PLL Setting Register ...................................................................................... 83
4.1.1.33 Chip ID Register ........................................................................................................... 84
4.1.1.34 Protocol Engine PLL Setting Register (PE PLL Register) ............................................ 85
4.1.1.35 Common Control Register ............................................................................................ 86
4.1.1.36 Interrupt Register Indirection ........................................................................................ 88
4.1.1.37 Ingress PE Settings Register (INGRESS_PE_INTERFACE (IPI) - Receive) ............... 89
4.1.1.38 Egress PE Setting Register (EGRESS_PE_INTERFACE - Transmit) ......................... 91
4.1.1.39 Common PE Setting Register (PE (Common)) ............................................................ 93
4.1.1.40 Parity and CRC Error Count Register (PARITY_Error_Count) ..................................... 95
5. IBM Packet Routing Switch Serial Interface Converter Latency ........................... 96
6. JTAG Description ...................................................................................................... 97
7. I/O Definition and Package Pin Assignment ........................................................... 99
7.1 Signals Description ....................................................................................................................... 99
7.2 I/O Timing ..................................................................................................................................... 112
7.2.1 IBM Packet Routing Switch Serial Interface Converter A.C. Characteristics ....................... 112
7.2.1.1 AC parameters characteristics ..................................................................................... 112
7.2.1.2 Protocol Engine (UTOPIA-3 like) Interface A.C. Specifications .................................... 112
7.2.1.3 Microprocessor Interface A.C. Specifications ............................................................... 113
8. Electrical Specifications ......................................................................................... 114
8.1 Power Sequencing ...................................................................................................................... 114
8.2 Recommended Operating Conditions ....................................................................................... 115
8.3 Signal Pin Assignments ............................................................................................................. 117
8.4 Power Signals .............................................................................................................................. 125
9. Packaging Information ............................................................................................ 128
10. Appendix A: Data Aligned Serial Link (DASL) .................................................... 129
10.1 General Description .................................................................................................................. 129
10.2 Resets ......................................................................................................................................... 133
10.3 Picocode Download .................................................................................................................. 133
10.3.1 Picocode Write ................................................................................................................... 133
10.3.2 Picocode Read ................................................................................................................... 133