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| 型號： | IBM3209K3114 |
| 廠商： | IBM Microeletronics |
| 英文描述： | IBM Packet Routing Switch Serial Interface Converter(IBM封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器) |
| 中文描述： | IBM的分組路由交換機串行接口轉(zhuǎn)換器（IBM的封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器） |
| 文件頁數(shù)： | 109/152頁 |
| 文件大?。?/td> | 2390K |
| 代理商： | IBM3209K3114 |
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IBM3209K3114
Advance
IBM Packet Routing Switch Serial Interface Converter
prssi.01
July 12, 2000
I/O Definition and Package Pin Assignment
Page 99 of 142
7. I/O Definition and Package Pin Assignment
7.1 Signals Description
All functional signals are 3.3 V LVTTL compatible for drivers and receivers except the following:
Protocol engine interface
Protocol engine clocks provided by the IBM Packet Routing Switch Serial Interface Converter
Back pressure serial link
LSDD and JTAG test signals
These are based on the tri-state driver/receiver (BP2550 type) that interfaces 2.5 V internal functions with 3.3
V-tolerant 2.5 V CMOS drivers and receivers off chip bidirectional data buses. The driver is 50
source-
terminated.
The switch fabric clocks are balanced HSTL levels.
Table 20: Tests Signals
Name
Input/
Output
Levels
Description
Notes
DI1
LVCMOS
Non-test driver inhibit for all chip boundary outputs.
0
Chip boundary outputs are disabled and in tri-state.
1
Inactive, all boundary outputs are controlled by normal functions. An
internal pull-up resistor forces the inactive state.
Boundary outputs are chip outputs or common I/O
’
s that serve as primary
outputs of the internal boundary logic. Feed directly by boundary latches or
special boundary logic books that make up the boundary logic.
DI2
Input
LVCMOS
The test driver inhibit for all chip non-boundary outputs.
0
Chip non-boundary outputs are disabled and in tri-state. An internal
pull-up resistor forces the inactive state.
1
Inactive, all non-boundary outputs are controlled by normal func-
tions.
Non-boundary outputs are chip outputs or common I/O
’
s that bring test func-
tion and LSSD scan data directly to and from the internal boundary logic.
RI
Input
LVCMOS
Gates all boundary receivers during internal test to prevent unknown states
from entering the internal logic and to reduce switching activities. RI pad
must be tied up externally for system mode. When active, all boundary
receivers are placed in a known state independent of the receiver input.
CE1_A
Input
LVCMOS
External source of the internal SRL scan A clock used during LSSD test to
enable the tester to independently source the internal SRL clocks from the
primary inputs.
1
CE1_B
Input
LVCMOS
External source of the internal SRL scan B clock used during LSSD test to
enable the tester to independently source the internal SRL clocks from the
primary inputs.
1
TEST_B2
Input
LVTTL
External source of the internal SRL scan B clock used during LSSD test to
enable the tester to independently source the internal SRL clocks from the
primary inputs.
1
CE1_C1
Input
LVCMOS
External source of the internal SRL scan C clock used during LSSD test to
enable the tester to independently source the internal SRL clocks from the
primary inputs (used for logic).
1
1. An internal pull-up resistor forces the inactive state.
2. Must be kept LOW during normal PLL operation.
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