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參數(shù)資料
| 型號(hào)： | IBM3209K3114 |
| 廠商： | IBM Microeletronics |
| 英文描述： | IBM Packet Routing Switch Serial Interface Converter(IBM封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器) |
| 中文描述： | IBM的分組路由交換機(jī)串行接口轉(zhuǎn)換器（IBM的封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 14/152頁(yè) |
| 文件大?。?/td> | 2390K |
| 代理商： | IBM3209K3114 |
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IBM3209K3114
IBM Packet Routing Switch Serial Interface Converter
Advance
Converter Ingress/Egress Data Flow
Page 4 of 142
prssi.01
July 12, 2000
2.1.5 Data Aligned Serial Link (DASL) Port Serializer
The IDI feeds the DASL port serializer with packets compatible with the switch LU format. (The 16 - 20 byte
LU width is set in the configuration register.) The DASL port serializer performs a multi-bit serialization for
each LU. Each serial DASL interface line represents a nibble of the LU, so there are two DASL links per byte.
The converter provides a total of eight serial links per port (one for each 4-bit nibble) representing a 32-bit
wide word.
2.1.6 Egress Data Flow
2.1.7 Data Aligned Serial Link (DASL) Port Deserializer
The DASL egress performs 32-bit deserialization on incoming data and builds LUs for the DASL egress inter-
face. It continuously monitors signal quality on the incoming high speed serial link and performs continuous
bit positioning adjustment on the incoming data to maintain synchronization.
2.1.8 Egress Data Aligned Serial Link Interface (EDI)
The DASL
’
s Receive Data Indicator line triggers the LU deserializer logic block which receives a continuous
stream of packets. Packet length is programmable from 64 to 80 bytes and is mapped on 4-bytes word
boundaries. Therefore, a new packet is received from the DASL every 16 to 20 cycles.
The LU deserializer extracts the switch packet header from the master LU to determine packet type (idle or
data) and priority. Idle packets are discarded. Data packets are forwarded (LU format) to the egress buffer
interface. The LU deserializer checks the LU CRC after each idle cell, the parity on the switch header, and the
type of packet. When an error or yellow packet is detected, and the checker is enabled, the corresponding
converter interrupt line is asserted.
2.1.9 Egress FIFO
The egress FIFO interface ignores any idle packets issued from the switch. Only data packets are pushed
into the transmit FIFOs (TXFIFOs) for a further word formatting packet operation. The TXFIFOs provide
packet synchronization between the 110 - 125 MHz converter and the 50 - 110 MHz protocol engine.
2.1.10 Egress Path Selection
The egress path selection multiplexes packets coming from the X and Y paths to the protocol engine
’
s egress
interface bus.The data is selected from the path in service through two interface lines (X_InService and
Y_InService) received from the switch core.
2.1.11 Egress Transmit Framing
The packet formatter translates custom formatted packet LUs, reversing the operation performed in the
ingress path. Header byte swapping moves the header bytes back to their original position. The converter
simultaneously takes the latest available output queue grant flow control data from the EDI and moves it into
the corresponding byte positions that were used for output port addressing in the ingress path. The most
recent shared memory grant and the output queue grant (OQG) priority (related to the bit map field
’
s OQG)
are both stored in the packet qualifier byte that is sent to the PE so it can perform virtual output queuing
scheduling for the ingress packets. Idle packets are also generated and sent to the PE in order to maintain
continuous flow control information.
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