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參數資料
| 型號： | IBM3209K3114 |
| 廠商： | IBM Microeletronics |
| 英文描述： | IBM Packet Routing Switch Serial Interface Converter(IBM封裝路線選擇開關串行接口轉換器) |
| 中文描述： | IBM的分組路由交換機串行接口轉換器（IBM的封裝路線選擇開關串行接口轉換器） |
| 文件頁數： | 143/152頁 |
| 文件大小： | 2390K |
| 代理商： | IBM3209K3114 |
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IBM3209K3114
Advance
IBM Packet Routing Switch Serial Interface Converter
prssi.01
July 12, 2000
Appendix A: Data Aligned Serial Link (DASL)
Page 133 of 142
10.2 Resets
SDC_RESET: (M3 Reset)
The DASL processor reset must be active during picocode download. It is recommended to activate
SDC_RESET during DASL reset (CORE_RESET).
CORE_RESET: (DASL Reset)
CORE_RESET signal resets the DASL. To insure proper reset, it is recommended to maintain the
CORE_RESET signal during at least 500 ns.
Both SDC_RESET and CORE_RESET signals are synchronous resets, and therefore need the presence of a
clock to be performed.
10.3 Picocode Download
The Instruction Memory for the DASL Shared Controller is accessible through the SDC Internal Resource
Interface (SDCIRI). The processor is given a separate reset so that it can be disabled until the Instruction
Memory is loaded. The SDC_RESET signal must be held active until Instruction Memory is completely
loaded. Once the picocode is completely loaded, release the SDC_RESET to start the processor.
10.3.1 Picocode Write
A picocode write operation is performed using the M3 picocode access register @40 for X plane and @60 for
Y plane. Data Instruction, Instruction Memory Address, and Write Enable bits must be written in the SDC
access register. The hardware handles the transfer in the Instruction Memory. Contiguous operations can be
performed until the picocode is completely downloaded.
10.3.2 Picocode Read
A picocode read operation is performed using the M3 picocode access register @40 for X plane and @60 for
Y plane. Instruction Memory Address and Read Enable bits must be written in the SDC access register. The
hardware handles the read operation.
The SDC access register shall be polled until the Read Completed bit is detected to be ON (active high).
When this bit is ON, the data contained in the SDC access register is valid and correspond to the selected
Instruction Memory Address.
10.4 SDC_INTERRUPT Signal
A high level on SDC_INTERRUPT (M3 interruption in registers 10 and 30) denotes an interrupt or a parity
error condition. If a parity error is detected on the instruction memory or the local data store, an interrupt will
be generated and remain active until the Shared DASL Controller is reset.
10.5 SDC Debug Interface
The SDC debug interface allows the application read and write access to any of the resources available to the
processor. Access includes local store, sample memory, and any hardware-assist registers addressable by
the processor (access to instruction memory is provided through SDC Internal Resource Interface). The inter-
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