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參數(shù)資料
| 型號(hào)： | IBM3209K3114 |
| 廠商： | IBM Microeletronics |
| 英文描述： | IBM Packet Routing Switch Serial Interface Converter(IBM封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器) |
| 中文描述： | IBM的分組路由交換機(jī)串行接口轉(zhuǎn)換器（IBM的封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器） |
| 文件頁數(shù)： | 11/152頁 |
| 文件大小： | 2390K |
| 代理商： | IBM3209K3114 |
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prssi.01
July 12, 2000
IBM3209K3114
Advance
IBM Packet Routing Switch Serial Interface Converter
General Information
Page 1 of 142
1. General Information
1.1 Features
Companion to the IBM 28.4 G Packet Routing
Switch
Support for internal (8 ports) and external (16
ports) switch speed expansion mode
Proprietary 440 Mbps, 8 HSTL pair, data aligned
serial link (DASL) switch interface
3.52 Gbps aggregate throughput per speed
expanded port
32-bit Ingress/Egress Protocol Engine Interface
Bus (UTOPIA-3 like bus)
Implements switch plane redundancy system
architecture with two independent paths
3 packet ingress/6 packet egress shared buffers
Implements In Band Flow Control (IBFC) via
packet header information
Up to four priority levels packet handling
Programmable Packet Length (64 to 80 bytes)
Link liveness packet insertion (Yellow packet)
8-bit Processor Interface (with bursting option)
Internal ABIST
IEEE 1149.1 standard boundary scan to facili-
tate circuit board testing
1.5 V DASL differential I/Os for DASLs
2.5 V Supply Voltage (3.3 V-tolerant I/Os) and
3.3 V LVTTL for the other signal I/Os
360 CBGA package
IBM CMOS 6 SF SA-12E technology
1.2 Description
The IBM Packet Routing Switch Serial Interface
Converter (the converter) is a companion chip to the
IBM 28.4 G Packet Routing Switch (the switch),
which connects the switch’s serial link to a protocol
engine (PE) on a 32-bit interface bus. The converter
attaches to a switch port operating in speed expan-
sion mode up to 4 Gbps, wired on eight DASL pairs
running at up to 500 Mbps per pair.
No synchronization is required between input ports.
However, packets on a given port are always
received or transmitted at a fixed interval equal to
the packet length. The converter ingress/egress
packet length is programmable from 64 to 80 bytes
in increments of four bytes. Input/Output packets to/
from the switch are mapped into 4x logical units (LU)
of 16 to 20 bytes depending upon the packet length.
The converter is composed of two fully independent
data paths (X and Y) to provide a resilient switch
fabric.These paths are clocked, reset and controlled
independently to support independent activation/
deactivation of each switch plane.
Ingress traffic (packets received from a PE interface
bus) is routed to both X and Y path switch planes,
thereby duplicating packets on both planes. Egress
traffic (packets received from switch plane X or Y) is
routed to a bus.
The converter normally uses In Band Flow Control
(IBFC). The continuous flow of packets transmits
necessary information to regulate packet traffic
between the PE and the switch planes (in band
signalling). Out of Band Flow Control (OBFC) may
also be used with IBFC at the interface level, using
the traditional operation UTOPIA-3 handshake
signals.
The converter extracts output queue grant informa-
tion from the 16 output queues of the switch, and
Memory Grant information corresponding to the four
priority watermark levels of the total shared memory.
It then provides this congestion control information
to the attached PE through an IBFC mechanism.
The information is transmitted to the PE in the
packet header bytes of either data or idle packets.
.
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