參數(shù)資料
型號： IBM3209K3114
廠商： IBM Microeletronics
英文描述： IBM Packet Routing Switch Serial Interface Converter(IBM封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器)
中文描述： IBM的分組路由交換機串行接口轉(zhuǎn)換器（IBM的封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器）
文件頁數(shù)： 110/152頁
文件大?。?/td> 2390K
代理商： IBM3209K3114
IBM3209K3114
IBM Packet Routing Switch Serial Interface Converter
Advance
I/O Definition and Package Pin Assignment
Page 100 of 142
prssi.01
July 12, 2000
CE1_C2
Input
LVCMOS
External source of the internal SRL scan C clock used during LSSD test to
enable the tester to independently source the internal SRL clocks from the
primary inputs (used for RAMS).
1
CE0_IO
Input
LVCMOS
Used to force the JTAG EXTEST operation for IBM test methodology pur-
poses.
1
CE0_Scan
Input
LVCMOS
Gates both the A and B LSSD test clocks.
1
CE0_TEST
Input
LVCMOS
Forces "0" in system mode and
‘
1
’
in LSSD test mode.
1
TEST_C3
Input
LVTTL
External source of the internal GRA scan C clock used during LSSD test to
enable the tester to independently source the internal GRA clocks from the
primary inputs.
1
PE_TESTIN
Input
LVCMOS
Programs the PLL to perform parametric testing at the wafer and module
level.
2
SWITCH_X_TESTIN
Input
LVCMOS
Programs the DASL PLL for fabric X to perform parametric testing at the
wafer and module levels.
2
SWITCH_Y_TESTIN
Input
LVCMOS
Programs the DASL PLL for fabric Y to perform parametric testing at the
wafer and module levels.
2
PE_TESTOUT
Output
LVCMOS
Monitor TESTOUT output during PLL test to verify the PLL output frequency.
SWITCH_X_TESTOUT
Output
LVCMOS
Monitor TESTOUT output during PLL test to verify the PLL output frequency.
SWITCH_Y_TESTOUT
Output
LVCMOS
Monitor TESTOUT output during PLL test to verify the PLL output frequency.
ABIST_CLK
Input
LVCMOS
Connected to the ABIST controller STCLK input and used only during test
operation. Keep this signal inactive (tied to ground) during system mode to
reduce power consumption in the BIST logic.
ABIST_DIAGOUT
Output
LVTTL
Each SRAM DIAGOUT output is multiplexed to this ABIST_DIAGOUT PO to
observe the pass/fail flag of individual arrays during the ABIST diagnostic
mode. See register @8C bit 2 for X or Y result on that pin.
Table 21: JTAG Interface External Signals
Name
Input/Out-
put
Levels
Description
Notes
TCK
Input
3.3 V LVTTL receiver tri-state CIO Test Clock Input
1, 2
TMS
Input
3.3 V LVTTL receiver tri-state CIO Test Mode Select Input
1, 2
TDI
Input
3.3 V LVTTL receiver tri-state CIO Test Data Input
1, 2
TDO
Output
3.3 V LVTTL 50
tri-state CIO
Test Data Output
1, 2
TRST
Input
3.3 V LVTTL receiver tri-state CIO
Test Reset Input must be asserted during the power-on-reset to
reset the JTAG control logic.
1, 2
1. An internal pull-up resistor forces the inactive state
2. . See IEEE 1149.1 specification for details.
Table 20: Tests Signals
Name
Input/
Output
Levels
Description
Notes
1. An internal pull-up resistor forces the inactive state.
2. Must be kept LOW during normal PLL operation.
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