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| 型號： | IBM3209K3114 |
| 廠商： | IBM Microeletronics |
| 英文描述： | IBM Packet Routing Switch Serial Interface Converter(IBM封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器) |
| 中文描述： | IBM的分組路由交換機串行接口轉(zhuǎn)換器（IBM的封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器） |
| 文件頁數(shù)： | 7/152頁 |
| 文件大?。?/td> | 2390K |
| 代理商： | IBM3209K3114 |
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IBM3209K3114
IBM Packet Routing Switch Serial Interface Converter
Advance
Page v
prssi.01LOF.fm
July 10, 2000
List of Figures
Figure 1: Overall Switch Subsystem Configuration ....................................................................... 2
Figure 2: IBM Packet Routing Switch Serial Interface General Data Flow .................................... 2
Figure 3: Converter Functional Block Diagram .............................................................................. 6
Figure 4: Bit and Byte Notation ...................................................................................................... 7
Figure 5: Ingress Timing for RXENB Deasserted by Converter for 1 Clock Cycle ........................ 9
Figure 6: Ingress Timing for RXENB Deasserted by Converter for 3 Clock Cycles ..................... 10
Figure 7: Ingress Timing for RXPAV Deasserted by Protocol Engine for 1 Clock Cycle ............. 10
Figure 8: Ingress Timing for RXPAV Deasserted by Protocol Engine for 3 Clock Cycles ........... 11
Figure 9: Ingress Packets in Back-to-Back from Protocol Engine ............................................... 11
Figure 10: TXFULL Timing .......................................................................................................... 14
Figure 11: Egress Timing for Back-to-Back Packets ................................................................... 14
Figure 12: Example of Converter Ingress Idle Packet ................................................................. 18
Figure 13: Example of Converter Egress Idle Packet .................................................................. 20
Figure 14: IBM 28.4 Packet Routing Switch (switch) Packet Qualifier Bits Reshuffling ............... 22
Figure 15: Path Selection ............................................................................................................ 24
Figure 16: Converter Interface Lines ........................................................................................... 30
Figure 17: Configuration in Normal Operating Mode ................................................................... 31
Figure 18: Protocol Engine Loopback Through Path X or Path Y ............................................... 31
Figure 19: Protocol Engine External Loopback Through Path X ................................................. 32
Figure 20: Switch X Loopback ..................................................................................................... 33
Figure 21: Clocks Distribution Diagram ....................................................................................... 34
Figure 22: IBM Packet Routing Switch Serial Interface Converter Processor Interface Lines ..... 39
Figure 23: Processor Read Access in 32-bit Burst Mode ............................................................ 40
Figure 24: Processor Write Access in 32-bit Burst Mode ............................................................ 40
Figure 25: Processor Read Access in 8-bit Byte Mode ............................................................... 41
Figure 26: Processor Write Access in 8-bit Byte Mode ............................................................... 41
Figure 27: Register Mapping ....................................................................................................... 42
Figure 28: Register Addressing ................................................................................................... 42
Figure 29: DI and Data Aligned Serial Link (DASL) Startup Sequence Path X ........................... 52
Figure 30: Enabling of Data Aligned Serial Link (DASL) Data Transmission and Reception Path X
52
Figure 31: DI and Data Aligned Serial Link (DASL) Startup Sequence Path Y ........................... 59
Figure 32: Enabling of Data Aligned Serial Link (DASL) Data Transmission and Reception Path Y
59
Figure 33: Converter Latency Diagram ........................................................................................ 96
Figure 34: Detection of Line Card Fully Inserted ....................................................................... 103
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