參數(shù)資料
型號： HYB18T256324F-20
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256-Mbit GDDR3 DRAM [600MHz]
中文描述： 256兆GDDR3顯示內(nèi)存[600MHz的]
文件頁數(shù)： 74/80頁
文件大?。?/td> 2026K
代理商： HYB18T256324F-20
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
Data Sheet
74
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
1. Data Bus consists of DQ, DM, WDQS
2. Definitions for IDD : LOW is defined as VIN = 0.4 x
V
DDQ
; HIGH is defined as
V
IN
=
V
DDQ
;
STABLE is defined as inputs are stable at a HIGH level.
SWITCHING is defined as inputs are changing between HIGH and LOW every clock cycle for address and
control signals, and inputs changing 50% of each data transfer for DQ signals.
3. Legend : A=Activate, RA=Read with Autoprecharge, D=DESELECT
I
DD2Q
Precharge Quiet Standby Current
CS is HIGH, all banks idle, CKE is HIGH,
t
CK
=min(
t
CK
), Address and other control inputs STABLE, Data
bus inputs are STABLE.
Active Power-Down Standby Current
All banks active, CKE is LOW, Address and control inputs are STABLE; Data bus inputs are STABLE;
standard active power-down mode.
Active Standby Current
All banks active, CS is HIGH, CKE is HIGH,
t
RC
=max(
t
RAS
),
t
CK
=min(
t
CK
); Address and control inputs
are SWITCHING; Data bus inputs are SWITCHING;
I
out
= 0 mA.
Operating Current - Burst Read
All banks active; Continuous read bursts, CL = CL(min);
t
CK=min(
t
CK
); Address and control inputs are
SWITCHING; Data bus inputs are SWITCHING.
Operating Current - Burst Write
All banks active; Continuous write bursts;
t
CK
=min(
t
CK
); Address and control inputs are SWITCHING;
Data bus inputs are SWITCHING.
Burst Auto Refresh Current
Refresh command at
t
RC
=min(
t
RFC
);
t
CK
=min(
t
CK
); CKE is HIGH, CS is HIGH between all valid
commands; Other command and address inputs are SWITCHING; Data bus inputs are SWITCHING.
Distributed Auto Refresh Current
tCK=tCKmin; Refresh command every tREFI; CKE is HIGH, CS is HIGH between valid commands;
Other command and address inputs are SWITCHING; Data bus inputs are SWITCHING.
Self Refresh Current
CKE
≤
max(
V
IL
), external clock off, CK and CK LOW; Address and control inputs are STABLE; Data
Bus inputs are STABLE.
Operating Bank Interleave Read Current
1. All banks interleaving with CL = CL(min); tRCD = tRCDRD(min); tRRD = tRRD(min); Iout=0mA;
Address and control inputs are STABLE during DESELECT; Data bus inputs are SWITCHING.
2: Timing pattern:
-1.6 (600 MHz, CL=7) :
t
CK
= 2.5ns,
t
RCDRD
= 7.
t
CK
;
t
RRD
= 4.
t
CK
;
t
RC
= 18.
t
CK
Read: A0 RA3 D D A1 D D RA0 A2 D D RA1 A3 D D RA2 D D TBD TBD TBD
-2.0 (500 MHz, CL7) :
t
CK
= 2.0ns,
t
RCDRD
= 7.
t
CK
;
t
RRD
= 4.
t
CK
;
t
RC
= 18.
t
CK
Read: A0 RA3 D D A1 D D RA0 A2 D D RA1 A3 D D RA2 D D
-2.2 (455 MHz, CL6) :
t
CK
= 2.2ns,
t
RCDRD
= 7.
t
CK
;
t
RRD
= 4.
t
CK
;
t
RC
= 18.
t
CK
Read: A0 RA3 D D A1 D D RA0 A2 D D RA1 A3 D D RA2 D D
I
DD3P
I
DD3N
I
DD4R
I
DD4W
I
DD5B
I
DD5D
I
DD6
I
DD7
Table 42
Symbol Parameter/Condition
Operating Current Measurement Conditions
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