參數(shù)資料
型號(hào): HYB18T256324F-20
廠商: INFINEON TECHNOLOGIES AG
英文描述: 256-Mbit GDDR3 DRAM [600MHz]
中文描述: 256兆GDDR3顯示內(nèi)存[600MHz的]
文件頁(yè)數(shù): 28/80頁(yè)
文件大小: 2026K
代理商: HYB18T256324F-20
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
28
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
3.4
Extended Mode Register Set Command (EMRS)
Figure 10
Extended Mode Register Bitmap
The Extended Mode Register is used to set the output
driver impedance value, the termination impedance
value, the Write Recovery time value for Write with
Autoprecharge. It is used as well to enable/disable the
DLL, to issue the Vendor ID and to enable/disable the
Low Power mode. There is no default value for the
Extended Mode Register. Therefore it must be written
after power up to operate the GDDR3 Graphics RAM.
The Extended Mode Register can be programmed by
performing a normal Mode Register Set operation and
setting the BA0 bit to HIGH. All other bits of the EMR
register are reserved and should be set to LOW.
The Extended Mode Register must be loaded when all
banks are idle and no burst are in progress. The
controller must wait the specified time
t
MRD
before
initiating any subsequent operation).
The timing of the EMRS command operation is
equivalent to the timing of the MRS command
operation.
Figure 11
Extended Mode Register Bitmap
1. Autocalibration is not supported for these settings.
2. Default termination values at Power Up.
#,+
#,+
2!3
#+%
#!3
7%
!!
"!
$ONgT#ARE
#/$#ODETOBELOADEDINTO
THEREGISTER
#3
#/$
"!
$ATA :
"!
"!
!
!
!
!
!
!
!
!
!
!
!
!
$,,
6
2&5
T
72!
2TT
!
,OW 0OWER
%NABLE
$ISABLE
!
!
/$4 DISABLED
2&5
4ERMINATION
:1
:1
$EFAULT
/UTPUT $RIVER
)MPEDANCE
!UTOCAL
/HM
/HM
/HM
!
!
T
72!
!
!
,0
!
6ENDOR )$
/N
/FF
!
$,,
%NABLE
%NABLE
$ISABLE
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