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參數(shù)資料
| 型號： | HYB18T256324F-20 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256-Mbit GDDR3 DRAM [600MHz] |
| 中文描述： | 256兆GDDR3顯示內(nèi)存[600MHz的] |
| 文件頁數(shù)： | 32/80頁 |
| 文件大小： | 2026K |
| 代理商： | HYB18T256324F-20 |
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HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
32
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
Figure 16
Mode Register Set Timing
1. This value of t
MRD
applies only to the case where the
“DLL reset” bit is not activated.
2. t
MRD
is defined from MRS to any other command as READ.
3.5.1
Read and Write accesses to the GDDR3 Graphics RAM are burst oriented with burst length 4. This value must be
programmed using the Mode Register Set command (A0 .. A2). The burst length determines the number of column
locations that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block if a boundary is reached. The block is uniquely selected by
A2-Ai where Ai is the most significant bit for a given configuration. The starting location within this block is
determined by the two least significant bits A0 and A1 which are set internally to the fixed value of zero each.
Reserved states should not be used, as unknow operation or incompatibility with future versions may result.
Burst length
3.5.2
Accesses within a given bank must be programmed to be sequential. This is done using the Mode Register Set
command (A3) . This device does not support the burst interleave mode.
Burst type
The value applied at the balls A0 and A1 for the column address is “Don’t care”.
Table 19
Parameter
MRS Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Symbol
Limit Values
–2.0
min
4
12
Unit
Notes
–1.6
–2.2
min
5
15
max
—
—
max
—
—
min
4
12
max
—
—
Mode Register Set cycle time
Mode Register Set to READ timing
t
MRD
t
MRDR
t
CK
t
CK
1, 2
1
#,+
#,+
0!
-23
./0
!#
./0
T
20
T
-2$
#OM
./0
2$
./0
$ONgT#ARE
-23-23COMMAND
0!02%!,,COMMAND
!#!NYOTHERCOMMANDAS2%!$
2$2%!$COMMAND
T
-2$2
Table 20
Burst Length
Burst Type
Starting Column address
Order of accesses within the burst
Type = Sequential
4
A1 A0
x x
0-1-2-3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB18T256324F-22 | 256-Mbit GDDR3 DRAM [600MHz] |
| HYB18T256400AFL-3 | 256 Mbi t DDR2 SDRAM |
| HYB18T256160A-3S | 256 Mbi t DDR2 SDRAM |
| HYB18T256800AFL-3 | 256 Mbi t DDR2 SDRAM |
| HYB18T256400AFL-37 | 256 Mbi t DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
| HYB18T256800AF-5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
| HYB18T512400AF-5 | 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA |
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