參數(shù)資料
型號： HYB18T256324F-20
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256-Mbit GDDR3 DRAM [600MHz]
中文描述： 256兆GDDR3顯示內(nèi)存[600MHz的]
文件頁數(shù)： 24/80頁
文件大小： 2026K
代理商： HYB18T256324F-20
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
24
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
3.3
Programmable impedance output drivers and active terminations
3.3.1
The GDDR3 SGRAM is equipped with programmable
impedance output buffers and active terminations. This
allows the user to match the driver impedance to the
system impedance.
To adjust the impedance of DQ<0:31> and
RDQS<0:3> , an external precision resistor (ZQ) is
connected between the ZQ pin and VSS. The value of
the resitor must be six times the value of the desired
impedance. For example, a 240
resistor is required
for an output impedance of 40
. The range of ZQ is
210
to 270
,
giving an output impedance range of
35
to 45
(one sixth the value of ZQ within 10%).
RES, CLK and CLK are not internally terminated.
The value of ZQ is used to calibrate the internal DQ
termination resistors of DQ<0:31>, WDQS<0:3> and
GDDR3 IO Driver and Termination
DM<0:3>. The two termination values that are
selectable using EMRS[3:2] are ZQ / 4 and ZQ / 2.
The value of ZQ is also used to calibrate the internal
address command termination resistors. The inputs
terminated in this manner are A<0:11>, CKE, CS, RAS,
CAS, WE. The two termination values that are
selectable upon power up (CKE latched a the LOW to
HIGH transition of RES) are ZQ/2 and ZQ.
The signals RES and CLK/CLK are not internally
terminated.
If no resistance is connected to ZQ, an internal default
value of 240
will be used. In this case, no calibration
will be performed.
Figure 6
Output Driver simplified schematic
Table 11
Parameter
External resistance value
Range of external resistance ZQ
Symbol
ZQ
min
210
nom
240
max
270
Unit
Notes
Table 12
Ball
CLK, CLK, RDQS<0:3>, ZQ, RES
CKE, CS, RAS, CAS, WE, BA<0:1>, A<0:11>
DM<0:3>, WDQS<0:3>,
DQ<0:31>
Termination types and activation
Termination type
No termination
Add / CMDs
DQ
DQ
Termination activation
Always ON
Always ON
CMD bus snooping
VSSQ
VDDQ
DQ
Read to
other Rank
Output Data
Read Data
Enable
ZQ/4 or ZQ/2
Terminator when
receiving
ZQ/6 Driver
when transmitting
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