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參數(shù)資料
| 型號： | HYB18T256324F-20 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256-Mbit GDDR3 DRAM [600MHz] |
| 中文描述： | 256兆GDDR3顯示內(nèi)存[600MHz的] |
| 文件頁數(shù)： | 10/80頁 |
| 文件大?。?/td> | 2026K |
| 代理商： | HYB18T256324F-20 |
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HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Overview
Data Sheet
10
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
1.2
General Description
The Infineon 256-Mbit GDDR3 DRAM [600MHz]is a
high speed memory device, designed for high
bandwidth intensive applications like PC graphics
systems. The chip’s quad bank architecture is
optimized for high speed and achieves a peak
bandwidth of 8 Gbyte/s using a 32 bit interface and a
maximum system clock of 600 MHz.
HYB18T256324F–[16/20/22] uses a double data rate
interface and a 4
n
-prefetch architecture. The GDDR3
interface transfers two 32 bit wide data words per clock
cycle to/from the I/O pins. Corresponding to the 4
n
-
prefetch a single write or read access consists of a 128
bit wide, one-clock-cycle data transfer at the internal
memory core and four corresponding 32 bit wide, one-
half-clock-cycle data transfers at the I/O pins.
Single-ended unidirectional Read and Write Data
strobes are transmitted simultaneously with Read and
Write data respectively in order to capture data properly
at the receivers of both the Graphics SDRAM and the
controller. Data strobes are organized per byte of the
32 bit wide interface. For read commands the RDQS
are edge-aligned with data, and the WDQS are center-
aligned with data for write commands.
The HYB18T256324F–[16/20/22] operates from a
differential clock (CLK and CLK). Commands
(addresses and control signals) are registered at every
positive edge of CLK. Input data is registered on both
edges of WDQS, and output data is referenced to both
edges of RDQS.
In this document references to ’the positive edge of
CLK’ imply the crossing of the positive edge of CLK and
the negative edge of CLK. Similarly, the ’negative edge
of CLK’ refers to the crossing of the negative edge of
CLK and the positive edge of CLK. References to
RDQS are to be interpreted as any or all RDQS<3:0>.
WDQS, DM and DQ should be interpreted in a similar
fashion.
Read and write accesses to the HYB18T256324F–
[16/20/22] are burst oriented. The burst length is fixed
to 4 and the two least significant bits of the burst
address are ’Don’t Care’ and internally set to LOW.
Accesses begin with the registration of an ACTIVATE
command, which is then followed by a READ or WRITE
command. The address bits registered coincident with
the ACTIVATE command are used to select the bank
and the row to be accessed. The address bits
registered coincident with the READ or WRITE
command are used to select the bank and the column
location for the burst access. Each of the 4 banks
consists of 4096 row locations and 512 column
locations. An AUTO PRECHARGE function can be
combined with READ and WRITE to provide a self-
timed row precharge that is initiated at the end of the
burst access. The pipelined, multibank architecture of
the HYB18T256324F–[16/20/22] allows for concurrent
operation, thereby providing high effective bandwidth
by hiding row precharge and activation time.
The device is supplied with 2.0 V for output drivers and
core. (
V
DD
/
V
DDQ
voltages see
Table 1
)
The “On Die Termination” interface (ODT) is optimized
for high frequency digital data transfers and is internally
controlled. The termination resistor value can be set
using an external ZQ resistor or disabled through the
Extended Mode Register.
The output driver impedance can be set using the
Extended Mode Register. It can either be set to ZQ / 6
(autocalibration) or to 35, 40 or 45 Ohms.
Auto Refresh and Power Down with Self Refresh
operations are supported.
A standard P-TBGA 144 package is used which
enables ultra high speed data transfer rates and a
simple upgrade path from former DDR Graphics
SDRAM products.
Table 2
Part Number
1)
HYB18T256324F–16
HYB18T256324F–20
HYB18T256324F–22
Ordering Information
1) HYB: designator for memory components
256: 256-Mbit density
32: 32 bit interface
4: Die Revision
F: Green Product
Organisation
×
32
V
DD
/
V
DDQ
(V)
2.0
2.0
2.0
Clock (MHz) Package
600
500
455
P-TBGA 144
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB18T256324F-22 | 256-Mbit GDDR3 DRAM [600MHz] |
| HYB18T256400AFL-3 | 256 Mbi t DDR2 SDRAM |
| HYB18T256160A-3S | 256 Mbi t DDR2 SDRAM |
| HYB18T256800AFL-3 | 256 Mbi t DDR2 SDRAM |
| HYB18T256400AFL-37 | 256 Mbi t DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
| HYB18T256800AF-5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
| HYB18T512400AF-5 | 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA |
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