參數(shù)資料
型號(hào)： HYB18T256324F-20
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256-Mbit GDDR3 DRAM [600MHz]
中文描述： 256兆GDDR3顯示內(nèi)存[600MHz的]
文件頁(yè)數(shù)： 18/80頁(yè)
文件大?。?/td> 2026K
代理商： HYB18T256324F-20
2 . t
CK
(CL + 4 - WL) . t
CK
t
CK
t
CK
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
Data Sheet
18
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
PWDNEX
A CKE HIGH value sampled at a low to high transition of CLK is required to exit power down mode.
Once CKE is HIGH, the GDDR3 Graphics RAM must receive only NOP/DESEL commands until t
XPN
is satisfied. After t
XPN
any command can be issued, but it has to comply with the state in which the
power down mode was entered.
Data Termination Disable (Bus snooping for RD commands) : The Data Termination Disable
Command is detected by the device by snooping the bus for RD commands excluding CS. The
GDDR3 Graphics RAM will disable its Data terminators when a RD command is detected. The
terminators are disabled starting at CL - 1 clocks after the RD command is detected and the duration
is 4 clocks. In a two rank system, both DRAM devices will snoop the bus for RD commands to either
device and both will disable their terminators if a RD command is detected. The command and
address terminators are always enabled. See
Figure 9
for an example of when the data terminators
are disabled during a RD command.
DTERDIS
Table 6
Minimum delay from RD/A and WR/A to any other command (to another bank) with concurrent
Autoprecharge
From Command
To Command
Minimum delay to another bank
(with concurrent autoprecharge)
WR/A
RD or RD/A
(WL + 2) . t
CK
+ t
WTR
WR or WR/A
2 . t
CK
PRE
t
CK
ACT
t
CK
RD/A
RD or RD/A
WR or WR/A
PRE
ACT
Note
Table 5
Command
Description of Commands
Description
相關(guān)PDF資料
PDF描述
HYB18T256324F-22 256-Mbit GDDR3 DRAM [600MHz]
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