參數(shù)資料
型號(hào): HYB18T256324F-20
廠商: INFINEON TECHNOLOGIES AG
英文描述: 256-Mbit GDDR3 DRAM [600MHz]
中文描述: 256兆GDDR3顯示內(nèi)存[600MHz的]
文件頁(yè)數(shù): 15/80頁(yè)
文件大小: 2026K
代理商: HYB18T256324F-20
L
L
L
L
L
L
H
L
X
L
X
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
Data Sheet
15
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
2.3
Commands
2.3.1
In the following table CKEn refers to the positive edge of CLK corresponding to the clock cycle when the command
is given to the Graphics SDRAM. CKEn-1 refers to the previous positive edge of CLK. For all command and
address inputs CKEn is implied.
All input states or sequences not shown are illegal or reserved.
Command Table
1. X represents “Don’t Care”.
2. BA0 and BA1 provide bank address, A0 - A11
provide the row address.
3. BA0 and BA1 provide bank address, A2- A7, A9
provide the column address, A8/AP controls Auto
Precharge.
4. Auto Refresh and Self Refresh Entry differ only by
the state of CKE
5. PWDNEN is selected by issuing a DESEL or NOP
at the first positive CLK edge following the HIGH to
LOW transition of CKE.
6. First possible valid command after
t
XPN
. During
t
XPN
only NOP or DESEL commands are allowed.
7. Self Refresh is selected by issuing AREF at the first
positive CLK edge following the HIGH to LOW
transition of CKE.
8. First possible valid command after
t
XSC
. During
t
XSC
only NOP or DESEL commands are allowed.
9. This command is invoked when a Read is issued on
another DRAM rank placed on the same command
bus. Cannot be in power-down or self-refresh state.
The Read command will cause the data termination
to be disabled. Refer to for timing.
Abbreviations:
BA:Bank Address
Col.:Column Address
Table 4
Operation
Command Overview
Code
CKE
n-1
H
CKE
n
H
CS
RAS CAS
WE
BA0 BA1 A8
A2-7
A9-11
X
Note
Device Deselect
DESEL
H
L
X
H
H
H
L
L
X
X
H
L
H
L
L
X
L
H
H
H
L
L
X
X
X
1
Data Terminator Disable
No Operation
Mode Register Set
Extended Mode Register
Set
Bank Activate
DTERDIS
NOP
MRS
EMRS
H
H
H
H
H
H
H
H
H
L
L
L
X
X
0
1
X
X
0
0
X
X
OPCODE
OPCODE
X
X
1,9
ACT
H
H
L
L
H
H
BA
BA
Row
Address
L
H
L
H
L
H
X
X
1,2
Read
Read w/ Autoprecharge
Write
Write w/ Autoprecharge
Precharge
Precharge All
Auto Refresh
Power Down Mode Entry
RD
RD/A
WR
WR/A
PRE
PREALL
AREF
PWDNEN H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
L
L
L
X
H
X
L
X
L
L
L
L
H
H
L
X
H
X
L
X
H
H
L
L
L
L
H
X
H
X
H
X
BA
BA
BA
BA
BA
X
X
X
BA
BA
BA
BA
BA
X
X
X
Col.
Col.
Col.
Col.
X
X
X
X
1,3
1,3
1,3
1,3
1
1
1,4
1,5
Power Down Mode Exit
Self Refresh Entry
Self Refresh Exit
PWDNEX
SREFEN
SREFEX
L
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
1,6
1,7
1,8
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