參數(shù)資料
型號(hào)： HYB18T256324F-20
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256-Mbit GDDR3 DRAM [600MHz]
中文描述： 256兆GDDR3顯示內(nèi)存[600MHz的]
文件頁(yè)數(shù)： 23/80頁(yè)
文件大?。?/td> 2026K
代理商： HYB18T256324F-20
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
23
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
3.2
Initialization
The HYB18T256324F–[16/20/22] must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation or permanent damage to the device.
The following sequence is highly recommended for Power-Up:
1. Apply power (
V
DD
,
V
DDQ
,
V
REF
). Apply
V
DD
before or at the same time as V
DDQ
, apply V
DDQ
before or at the same
time as V
REF
. Maintain RES=L and CS=H to ensure that all the DQ ouputs will be in HiZ state, all active
terminations off and the DLL off. All other pins may be undefined.
2. Maintain stable conditions for 200
μ
s minimum for the GDDR3 Graphics RAM to power up.
3. After clock is stable, set CKE to L. After t
ATS
minimum set RES to high. On the rising edge of RES, the CKE
value is latched to determine the address and command bus termination value. If CKE is sampled LOW the
address termination value is set to ZQ / 2. If CKE is sampled HIGH, the address and command bus termination
is set to ZQ.
4. After t
ATH
minimum, set CKE to high.
5. Wait a minimum of 350 cycles to calibrate and update the address and command termination impedances.
Issue DESELECT on the command bus during these 350 cycles.
6. Apply a PRECHARGE ALL command, followed by an Extended Mode Register command after t
RP
is met and
activate the DLL.
7. Issue an Mode Register Set command after tMRD is met to reset the DLL and define the operating parameters.
8. Wait 200 cycles of clock input to lock the DLL. No Read command can be applied during this time. Since the
impedance calibration is already completed, the DLL mimic circuitry can use the actual programmed driver
impedance value.
9. Issue a PRECHARGE ALL command or issue 4 single bank PRECHARGE commands, one to each of the 4
banks to place the chip in an idle state.
10.Issue two or more AUTO REFRESH commands to update the driver impedance.
Figure 5
Power Up Sequence
Table 10
Parameter
Reset Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Symbol
Limit Values
–2.0
min
10
10
Unit
Notes
–1.6
–2.2
min
10
10
max
—
—
max
—
—
min
10
10
max
—
—
RES to CKE setup time
RES to CKE hold time
t
ATS
t
ATH
ns
ns
#,+
#,+
#+%
MIN
S
#OM
6$$
6$$1
62%&
2%3
T
!43
T
!4(
0!
%-
2
T
20
-23
T
-2$
!2&
!#
!2&
0!
T
2&#
T
2&#
T
20
CYCLES
MIN
6$$ AND
#,+ STABLE
$ONgT #ARE
0!
!2&
02%!,, COMMAND
!54/ 2%&2%3( COMMAND
!#
!NY COMMAND
T
-2$
CYCLES
MIN
$%3
$%3
-23 -23 COMMAND
WITH $,, 2ESET
%-2 %-23 COMMAND
$%3 $ESELECT
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