參數(shù)資料
型號(hào)： HYB18T256324F-20
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256-Mbit GDDR3 DRAM [600MHz]
中文描述： 256兆GDDR3顯示內(nèi)存[600MHz的]
文件頁(yè)數(shù)： 46/80頁(yè)
文件大?。?/td> 2026K
代理商： HYB18T256324F-20
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
46
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
3.8
Reads (RD)
3.8.1
Read - Basic Information
Figure 29
Read Command
Read bursts are initiated with a RD command, as
shown in
Figure 29
. The column and bank addresses
are provided with the RD command and Autoprecharge
is either enabled or disabled for that access. The length
of the burst initiated with a RD command is always four.
There is no interruption of RD bursts. The two least
significant start address bits are ’Don’t Care’.
If Autoprecharge is enabled, the row being accessed
will start precharge at the completion of the burst. The
begin of the internal Autoprecharge will always be one
cycle after
t
RAS
(min) is met.
During RD bursts the memory device drives the read
data edge aligned with the RDQS signal which is also
driven by the memory. After a programmable CAS
latency of 5, 6 or 7 the data is driven to the controller.
RDQS leaves HIGH state one cycle before its first rising
edge (RD preamble t
RPRE
). After the last falling edge of
RDQS a postamble of t
RPST
is performed.
t
AC
is the time between the positive edge of CLK and the
appearance of the corresponding driven read data. The
skew between RDQS and the crossing point of
CLK/CLK is specified as
t
DQSCK
.
t
AC
and
t
DQSCK
are
defined relatively to the positive edge
of CLK.
t
DQSQ
is
the skew between a RDQS edge and the last valid data
edge belonging to the RDQS edge.
t
DQSQ
is derived at
each RDQS edge and begins with RDQS transition and
ends with the last valid transition of DQs. t
QHS
is the
data hold skew factor and t
QH
is the time from the first
valid rising edge of RDQS to the first conforming DQ
going non-valid and it depends on t
HP
and t
QHS
. t
HP
is
the minimum of
t
CL
and
t
CH
.
t
QHS
is effectively the time
from the first data transition (before RDQS) to the
RDQS transition. The data valid window is derived for
each RDQS transition and is defined as
t
QH
minus
t
DQSQ
.
After completion of a burst, assuming no other
commands have been initiated, data will go High-Z and
RDQS will go HIGH. Back to back RD commands are
possible producing a continuous flow of output data.
There has to be one NOP cycle between back to back
RD commands.
Any RD burst may be followed by a subsequent WR
command. The minimum required number of NOP
commands between the RD command and the WR
command (
t
RTW
) depends on the programmed Read
latency and the programmed Write latency
t
RTW
(min)= (CL+4-WL)
Chapter 3.8.5
shows the timing requirements for RD
followed by a WR with some combinations of CL and
WL.
A RD may also be followed by a PRE command. Since
no interruption of bursts is allowed the minimum time
between a RD command and a PRE is two clock cycles
as shown in
Chapter 3.8.6
.
All timing parameters are defined with controller
terminations on.
#,+
#,+
2!3
#+%
#!3
7%
! !
!
"! "!
#!
"!
#! #OLUMN !DDRESS
"! "ANK !DDRESS
$ONgT #ARE
!
!
!
!
!
! 0
!0 !UTO0RECHARGE
#3
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