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| 型號： | HYB18T256324F-20 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256-Mbit GDDR3 DRAM [600MHz] |
| 中文描述： | 256兆GDDR3顯示內(nèi)存[600MHz的] |
| 文件頁數(shù)： | 61/80頁 |
| 文件大?。?/td> | 2026K |
| 代理商： | HYB18T256324F-20 |
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HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
61
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
3.11
Auto Refresh Command (AREF)
Figure 45
Auto Refresh Command
AREF is used to do a refresh cycle on one row in each
bank. The addresses are generated by an internal
refresh controller; external address pins are “DON’T
CARE”. All banks must be idle before the AREF
command can be applied. The delay between the
AREF command and the next ACT or subsequent
AREF must be at least
t
RFC
(min). The refresh period
starts when the AREF command is entered and ends
t
RFC
later at which time all banks will be in the idle state.
Within a period of
t
REF
=32ms the whole memory has to
be refreshed. The average periodic interval time from
AREF to AREF is then
t
REFI
(max)=7.8μs.
To improve efficiency bursts of AREF commands can
be used. Such bursts may consist of maximum 8 AREF
commands.
t
RFC
(min) is the minimum required time
between two AREF commands inside one AREF burst.
According to the number of AREF commands in one
burst the average required time from one AREF burst
to the next can be increased. Example: If the AREF
bursts consists of 4 AREF commands, the average
time from one AREF burst to the next is 4 * 7.8μs =
31.2μs.
The AREF command generates an update of the OCD
output impedance and of the addresses, commands
and DQ terminations. The timing parameter tKO ( see
section 2.3.2 ) must be complied with.
Figure 46
Auto Refresh Cycle
#,+
#,+
2!3
#+%
#!3
7%
! !
"! "!
"! "ANK !DDRESS
$ONgT #ARE
#3
Table 28
Parameter
Autorefresh Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Symbol
Limit Values
–2.0
min
—
7.8
54
Unit
Notes
–1.6
–2.2
min
—
max
32
7.8
—
max
32
min
—
max
32
7.8
—
Refresh Period (4096 cycles)
Average periodic Auto Refresh interval
Delay from AREF to next ACT/ AREF
t
REF
t
REFI
t
RFC
ms
μs
ns
54
—
54
#,+
#,+
!2&
. /0
T
20
T
2& #
#OMMAND
0 2%
#+%
./0
./0
!#
!2&
T
2%&
$ONgT #ARE
!2& !UTO 2EFRESH
!#
!2%& OR !#4 #OMMAND
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PDF描述 |
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| HYB18T256324F-22 | 256-Mbit GDDR3 DRAM [600MHz] |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
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| HYB18T256800AF-5 | 制造商:Infineon Technologies AG 功能描述: |
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| HYB18T512400AF-5 | 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA |
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