參數資料
型號: HYB18T256324F-20
廠商: INFINEON TECHNOLOGIES AG
英文描述: 256-Mbit GDDR3 DRAM [600MHz]
中文描述: 256兆GDDR3顯示內存[600MHz的]
文件頁數: 26/80頁
文件大小: 2026K
代理商: HYB18T256324F-20
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
26
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
Figure 8
represents a simplified schematic of the calibration circuits. First, the strength control bits are adjusted
in such a way that the
V
DDQ
voltage is divided equaly between the PMOS device and the ZQ resistor. The best bit
pattern will cause the comparator to switch the PMOS Match signal output value. In a second step, the NFET is
calibrated against the already calibrated PFET. In the same manner, the best control bit combination will cause
the comparator to switch the NMOS Match signal output value.
Figure 8
Self Calibration of PMOS and NMOS Legs
3.3.3
The GDDR3 Graphics RAM will disable its data terminators when a READ or DTERDIS command is detected. The
terminators are disabled starting at CL - 1 Clocks after the READ / DTERDIS command is detected and the
duration is 4 clocks. In a two rank system, both devices will snoop the bus for a READ / DTERDIS command to
either device and both will disable their terminators if a READ / DTERDIS command is detected. The address and
command terminators are always enabled.
Dynamic Switching of DQ terminations
VDDQ
Strength
Control [2:0]
VSSQ
Match
VDDQ / 2
ZQ
PMOS
Calibration
VSSQ
VDDQ
Strength
Control [2:0]
VSSQ
Match
VDDQ / 2
NMOS
Calibration
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