參數(shù)資料
型號: HYB18T256324F-20
廠商: INFINEON TECHNOLOGIES AG
英文描述: 256-Mbit GDDR3 DRAM [600MHz]
中文描述: 256兆GDDR3顯示內(nèi)存[600MHz的]
文件頁數(shù): 55/80頁
文件大?。?/td> 2026K
代理商: HYB18T256324F-20
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
55
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
3.9
Data Termination Disable (DTERDIS)
Figure 38
Data Termination Disable Command
The Data Termination Disable command is detected by
the device by snooping the bus for Read commands
when CS is high. The terminators are disabled starting
at CL - 1 clocks after the DTERDIS command is
detected and the duration is 4 clocks. The command
and address terminators are always enabled.
DTERDIS may only be applied to the GDDR3 Graphics
memory if it is not in the Power Down or in the Self
Refresh state.
The timing relationship between DTERDIS and other
commands is defined by the constraint to avoid
contention on the RDQS bus (i.e Read to DTERDIS
transistion) or the necessity to have a defined
termination on the data bus during Write (i.e. Write to
DTERDIS transition). ACT and PRE/PREALL may be
applied at any time before or after a DTERDIS
command.
Figure 39
DTERDIS Timing
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