- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄364671 > AM42BDS6408G 250NS, PGA, 883C; LEV B FULLY COMPLIANT(EEPROM) PDF資料下載
參數(shù)資料
| 型號： | AM42BDS6408G |
| 英文描述： | 250NS, PGA, 883C; LEV B FULLY COMPLIANT(EEPROM) |
| 中文描述： | Am42BDS6408G -堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁數(shù)： | 72/73頁 |
| 文件大?。?/td> | 1080K |
| 代理商： | AM42BDS6408G |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁當前第72頁第73頁
November 1, 2002
Am42BDS6408G
71
P R E L I M I N A R Y
REVISION SUMMARY
Revision A (February 27, 2002)
Initial release.
Revision B (May 10, 2002)
Connection Diagrams, Physical Dimensions
Changed ball count from 81 to 93.
Table 1, Device Bus Operations
Corrected CE1#s and CE2s columns.
Table 4, System Interface String
Corrected data for address 23h.
Table 9, Initial Access Codes
Changed title of table. Changed number of initial
access cycles for an even initial address burst
sequence from 1 to 2 cycles. Deleted Wait States for
Handshaking table.
Autoselect Command Sequence
Added bottom boot device IDs to table.
Table 13, Device IDs
Added bottom boot device IDs to table.
RDY: Ready
Corrected boundary address from 63rd/3Eh to
64th/3Fh.
Absolute Maximum Ratings, Operating Ranges
Added specification for V
IO
.
Flash DC Characteristics
Added V
IO
= V
IO
min
to test conditions for V
OL
and V
OH
in table.
SRAM DC Characteristics
Added specifications for V
IL
and V
IH
. Added notes 2 to
4. Changed specifications for I
CC1
s max, I
CC2
s max,
and I
SB1
.
Figure 8, Test Setup
Modified circuitry shown in figure.
Erase/Program Operations table
Added specifications for parameters t
CSW1
, t
CSW2
, t
CHW
,
t
AHC
.
Synchronous Burst Read table
Filled in specifications for 78 and 79 speed options.
Figure 21, Figure 23
Added note to indicate AVD# must toggle during
command sequence unlock cycles. Added t
CSW1
to
Figure 21.
Figure 22, Figure 24
Added figures, which show different timings between
addresses, CLK, WE#, and AVD#.
Figure 27, Figure 28, Figure 29
Added note to indicate AVD# must toggle during data
reads.
Figure 30, Figure 31
Shifted address, clock, and data cycle counts up by
one.
Figure 33 to Figure 36
Deleted references to CIOs.
Flash Erase and Programming Performance
Corrected maximum word program time.
SRAM AC Characteristics, Read Cycle and Write
Cycle tables
Added specifications for 85 ns SRAM.
Figure 36
In Data Out waveform, corrected t
BW
to t
WHZ
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM42DL16X2D | 150NS, CERDIP, 883C; LEV B COMPLIANT(EEPROM) |
| AM42DL16X4D | 150NS, PLCC, IND TEMP(EEPROM) |
| AM42DL32X4G | 150NS, 32LCC, 883C; LEV B COMPLIANT(EEPROM) |
| AM42DL6402G | 150NS, SOIC, IND TEMP(EEPROM) |
| AM42DL6404G | 64 Mbit (8 M x 8-Bit/4 M x 16-Bit) CMOS and 4 Mbit (256 K x 16-Bit) Static RAM (Preliminary) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM42BDS6408GBD8IT | 制造商:Spansion 功能描述:COMBO 4MX16 FLASH + 512KX16 SRAM 1.8V 93FBGA - Tape and Reel |
| AM42BDS6408GTD8I | 制造商:Spansion 功能描述:Combo Mem 4Mx16 Flash + 512Kx16 SRAM 1.8V 93-Pin FBGA |
| AM42BDS6408H | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory, and 8 Mbit (512 K x 16-Bit) SRAM |
| AM42BDS6408HD3I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory, and 8 Mbit (512 K x 16-Bit) SRAM |
| AM42BDS6408HD4I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory, and 8 Mbit (512 K x 16-Bit) SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。