參數資料
型號: AM42BDS6408G
英文描述: 250NS, PGA, 883C; LEV B FULLY COMPLIANT(EEPROM)
中文描述: Am42BDS6408G -堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁數: 2/73頁
文件大?。?/td> 1080K
代理商: AM42BDS6408G
PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
Publication#
26087
Issue Date:
November 1, 2002
Rev:
C
Amendment/
0
Am42BDS6408G
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29BDS640G 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation,
Burst Mode Flash Memory and 8 Mbit (512 K x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
Power supply voltage of 1.65 to 1.95 volt
High performance
— Access time as fast as 70 ns
Package
— 93-Ball FBGA
Operating Temperature
— –40°C to +85°C
Flash Memory Features
ARCHITECTURAL ADVANTAGES
Single 1.8 volt read, program and erase (1.65 to 1.95 volt)
Manufactured on 0.17 μm process technology
Simultaneous Read/Write operation
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
— Four bank architecture: 16Mb/16Mb/16Mb/16Mb
Programmable Burst Interface
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
— Continuous Sequential Burst
Sector Architecture
— Eight 8 Kword sectors and one hundred twenty-six 32
Kword sectors
— Banks A and D each contain four 8 Kword sectors and
thirty-one 32 Kword sectors; Banks B and C each contain
thirty-two 32 Kword sectors
— Eight 8 Kword boot sectors, four at the top of the address
range, and four at the bottom of the address range
Minimum 1 million erase cycle guarantee per sector
20-year data retention at 125°C
PERFORMANCE CHARCTERISTICS
Read access times at 54/40 MHz
— Burst access times of 13.5/20 ns @ 30 pF at industrial
temperature range
— Asynchronous random access times of 70 ns (at 30 pF)
— Synchronous latency of 87.5/95 ns
Power dissipation (typical values, C
L
= 30 pF)
— Burst Mode Read: 10 mA
— Simultaneous Operation: 25 mA
— Program/Erase: 15 mA
— Standby mode: 0.2 μA
HARDWARE FEATURES
Software command sector locking
Handshaking: host monitors operations via RDY output
Hardware reset input (RESET#)
WP# input
— Write protect (WP#) function protects sectors 0, 1 (bottom
boot) or sectors 132 and 133 (top boot), regardless of sector
protect status
ACC input: Acceleration function reduces programming
time; all sectors locked when ACC = V
IL
CMOS compatible inputs, CMOS compatible outputs
Low V
CC
write inhibit
SOFTWARE FEATURES
Supports Common Flash Memory Interface (CFI)
Software command set compatible with JEDEC 42.4
standards
Data# Polling and toggle bits
Erase Suspend/Resume
— Suspends or resumes an erase operation in one sector to
read data from, or program data to, other sectors
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
SRAM Features
Power dissipation
— Operating: 2 mA typical
— Standby: 0.2 μA typical
CE1s# and CE2s Chip Select
Power down features using CE1s# and CE2s
Data retention supply voltage: 1.0 to 2.2 volt
Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
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