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| 型號： | AM42BDS6408G |
| 英文描述： | 250NS, PGA, 883C; LEV B FULLY COMPLIANT(EEPROM) |
| 中文描述： | Am42BDS6408G -堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁數(shù)： | 58/73頁 |
| 文件大小： | 1080K |
| 代理商： | AM42BDS6408G |
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November 1, 2002
Am42BDS6408G
57
P R E L I M I N A R Y
AC CHARACTERISTICS
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to
determine status. When the Embedded Algorithm
operation is complete, and Data# Polling will output true
data.
3. AVD# must toggle between data reads.
Figure 27.
Data# Polling Timings (During Embedded Algorithm)
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to
determine status. When the Embedded Algorithm
operation is complete, the toggle bits will stop toggling.
3. AVD# must toggle between data reads.
Figure 28.
Toggle Bit Timings (During Embedded Algorithm)
WE#
CE#
OE#
t
OE
Addresses
AVD#
t
OEH
t
CE
t
CH
t
OEZ
t
CEZ
Status Data
Status Data
t
ACC
VA
VA
Data
WE#
CE#
OE#
t
OE
Addresses
Data
AVD#
t
OEH
t
CE
t
CH
t
OEZ
t
CEZ
Status Data
Status Data
t
ACC
VA
VA
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