參數(shù)資料
型號: AM42BDS6408G
英文描述: 250NS, PGA, 883C; LEV B FULLY COMPLIANT(EEPROM)
中文描述: Am42BDS6408G -堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁數(shù): 52/73頁
文件大?。?/td> 1080K
代理商: AM42BDS6408G
November 1, 2002
Am42BDS6408G
51
P R E L I M I N A R Y
AC CHARACTERISTICS
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid
Address for reading status bits.
2. “In progress” and “complete” refer to status of program
operation.
3. A21–A12 are don’t care during command sequence
unlock cycles.
4. CLK can be either V
IL
or V
IH
.
5. The Asynchronous programming operation is
independent of the Set Device Read Mode bit in the Burst
Mode Configuration Register.
6. AVD# must toggle during command sequence if CLK is at
V
IH
.
Figure 21.
Asynchronous Program Operation Timings
OE#
CE#
Data
Addresses
AVD#
WE#
CLK
V
CC
555h
PD
t
AS
t
AVSW
t
AVHW
t
CSW1
t
AH
t
WC
t
WPH
PA
t
VCS
t
WP
t
DH
t
CH
In
Progress
t
WHWH1
VA
Complete
VA
Program Command Sequence (last two cycles)
Read Status Data
t
DS
V
IH
V
IL
t
AVDP
A0h
t
CS
(Note 4)
(Note 6)
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