參數(shù)資料
型號： AM42BDS6408G
英文描述： 250NS, PGA, 883C; LEV B FULLY COMPLIANT(EEPROM)
中文描述： Am42BDS6408G -堆疊式多芯片封裝（MCP）閃存和SRAM
文件頁數(shù)： 5/73頁
文件大小： 1080K
代理商： AM42BDS6408G
4
Am42BDS6408G
November 1, 2002
P R E L I M I N A R Y
Figure 24. Alternate Synchronous ProgramOperation Timngs..... 54
Figure 25. Chip/Sector Erase Command Sequence....................... 55
Figure 26. Accelerated Unlock Bypass ProgrammngTimng......... 56
Figure 27. Data#Polling Timngs (DuringEmbeddedAlgorithm... 57
Figure 28. Toggle Bit Timngs (DuringEmbeddedAlgorithm......... 57
Figure 29. Synchronous Data Polling Timngs/Toggle Bit Timngs. 58
Figure 30. Latency with Boundary Crossing................................... 59
Figure 31. Latency with Boundary Crossing
into Program/Erase Bank................................................................ 60
Figure 32. Example of Wait States Insertion (Standard
HandshakingDevice)...................................................................... 61
Figure 33. Back-to-Back Read/Write Cycle Timngs....................... 62
SRAM AC Characteristics . . . . . . . . . . . . . . . . . . 63
Read Cycle .............................................................................63
Figure 34. SRAMRead Cycle—Address Controlled....................... 63
Figure 35. SRAMRead Cycle......................................................... 64
Write Cycle .............................................................................65
Figure 36. SRAMWrite Cycle—WE#Control................................. 65
Figure 37. SRAMWrite Cycle—CE1#s Control.............................. 66
Figure 38. SRAMWrite Cycle—UB#s and LB#s Control................ 67
Flash Erase And Programming Performance . . 68
Flash Latchup Characteristics. . . . . . . . . . . . . . . 68
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 68
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 68
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 69
Figure 39. CE1#s Controlled Data Retention Mode....................... 69
Figure 40. CE2s Controlled Data Retention Mode......................... 69
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 70
FLB093—93-Ball Fine-Pitch Grid Array 8 x 11.6 mm.............70
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 71
Revision A (February 27, 2002) ..............................................71
Table 9, Initial Access Codes ..............................................71
Autoselect Command Sequence .........................................71
RDY: Ready .........................................................................71
Absolute MaximumRatings, Operating Ranges ..................71
Flash DC Characteristics .....................................................71
SRAMDC Characteristics ...................................................71
Synchronous Burst Read table ............................................71
Figure 21, Figure 23 ............................................................71
Figure 22, Figure 24 ............................................................71
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