- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄364671 > AM42BDS6408G 250NS, PGA, 883C; LEV B FULLY COMPLIANT(EEPROM) PDF資料下載
參數(shù)資料
| 型號： | AM42BDS6408G |
| 英文描述： | 250NS, PGA, 883C; LEV B FULLY COMPLIANT(EEPROM) |
| 中文描述： | Am42BDS6408G -堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁數(shù)： | 44/73頁 |
| 文件大?。?/td> | 1080K |
| 代理商： | AM42BDS6408G |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當(dāng)前第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁
November 1, 2002
Am42BDS6408G
43
P R E L I M I N A R Y
AC CHARACTERISTICS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
4. A17 = 1.
Figure 13.
Synchronous Burst Mode Read
Note:
Figure assumes 7 wait states for initial access, 54 MHz clock, and automatic detect synchronous read. D0–D7 in data
waveform indicate the order of data within a given 8-word address range, from lowest to highest. Data will wrap around within
the 8 words non-stop unless the RESET# is asserted low, or AVD# latches in another address. Starting address in figure is the
7th address in range (A6). See “Requirements for Synchronous (Burst) Read Operation”. The Set Configuration Register
command sequence has been written with A18=1; device will output RDY with valid data.
Figure 14.
8-word Linear Burst with Wrap Around
Da
Da + 1
Da + n
OE#
DQ15
-
DQ0
A21
-
A0
Aa
AVD#
RDY
CLK
CE#
t
CAS
t
AAS
t
AVC
t
AVD
t
AAH
t
OE
t
RACC
t
OEZ
t
CEZ
t
IACC
t
BDH
7 cycles for initial access shown.
Hi-Z
Hi-Z
Hi-Z
1
2
3
4
5
6
7
t
RDYS
t
BACC
t
ACC
D6
D7
OE#
DQ15
-
DQ0
A21
-
A0
Aa
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVDS
t
AVD
t
ACH
t
OE
t
IACC
t
ACC
t
BDH
D0
D1
D5
D6
7 cycles for initial access shown.
18.5 ns typ. (54 MHz)
Hi-Z
t
RACC
1
2
3
4
5
6
7
t
RDYS
t
BACC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM42DL16X2D | 150NS, CERDIP, 883C; LEV B COMPLIANT(EEPROM) |
| AM42DL16X4D | 150NS, PLCC, IND TEMP(EEPROM) |
| AM42DL32X4G | 150NS, 32LCC, 883C; LEV B COMPLIANT(EEPROM) |
| AM42DL6402G | 150NS, SOIC, IND TEMP(EEPROM) |
| AM42DL6404G | 64 Mbit (8 M x 8-Bit/4 M x 16-Bit) CMOS and 4 Mbit (256 K x 16-Bit) Static RAM (Preliminary) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM42BDS6408GBD8IT | 制造商:Spansion 功能描述:COMBO 4MX16 FLASH + 512KX16 SRAM 1.8V 93FBGA - Tape and Reel |
| AM42BDS6408GTD8I | 制造商:Spansion 功能描述:Combo Mem 4Mx16 Flash + 512Kx16 SRAM 1.8V 93-Pin FBGA |
| AM42BDS6408H | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory, and 8 Mbit (512 K x 16-Bit) SRAM |
| AM42BDS6408HD3I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory, and 8 Mbit (512 K x 16-Bit) SRAM |
| AM42BDS6408HD4I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory, and 8 Mbit (512 K x 16-Bit) SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。