參數(shù)資料
型號: AM42BDS6408G
英文描述: 250NS, PGA, 883C; LEV B FULLY COMPLIANT(EEPROM)
中文描述: Am42BDS6408G -堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁數(shù): 10/73頁
文件大小: 1080K
代理商: AM42BDS6408G
November 1, 2002
Am42BDS6408G
9
P R E L I M I N A R Y
PIN DESCRIPTION
A18–A0
=
19 Address Inputs (Common)
A21–A19
=
3 Address Inputs (Flash)
DQ15–DQ0
=
16 Data Inputs/Outputs (Common)
CE#f
=
Chip Enable (Flash)
CE1#s
=
Chip Enable 1 (SRAM)
CE2s
=
Chip Enable 2 (SRAM)
OE#
=
Output Enable (Common)
WE#
=
Write Enable (Common)
UB#s
=
Upper Byte Control (SRAM)
LB#s
=
Lower Byte Control (SRAM)
RESET#
=
Hardware Reset Pin, Active Low
V
CC
f
=
Flash 1.8 volt-only single power
supply (see Product Selector Guide
for speed options and voltage sup-
ply tolerances)
V
IO
f
=
Input & Output Buffer Power Supply
must be tied to V
CC
.
SRAM Power Supply
V
CC
s
V
SSIO
f
V
SS
NC
=
=
Output Buffer Ground
=
Device Ground (Common)
=
Pin Not Connected Internally
RDY
=
Ready output; indicates the status of
the Burst read. Low = data not valid
at expected time. High = data valid.
CLK
=
CLK is not required in asynchronous
mode. In burst mode, after the initial
word is output, subsequent active
edges of CLK increment the internal
address counter.
AVD#
=
Address Valid input. Indicates to de-
vice that the valid address is present
on the address inputs (A21–A0).
Low = for asynchronous mode, indi-
cates valid address; for burst mode,
causes starting address to be
latched.
High = device ignores address in-
puts
WP#
=
Hardware write protect input. At V
IL
,
disables program and erase func-
tions in the two outermost sectors.
Should be at V
IH
for all other condi-
tions.
ACC
=
At V
ID
, accelerates programming;
automatically places device in un-
lock bypass mode. At V
IL
, locks all
sectors. Should be at V
IH
for all other
conditions.
LOGIC SYMBOL
19
16
DQ15–DQ0
A18–A0
CE#f
OE#
WE#
RESET#
UB#s
RDY
WP#
A21–A19
LB#s
ACC
CE1#s
CE2s
AVD#
CLK
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