- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄364671 > AM42BDS6408G 250NS, PGA, 883C; LEV B FULLY COMPLIANT(EEPROM) PDF資料下載
參數(shù)資料
| 型號(hào)： | AM42BDS6408G |
| 英文描述： | 250NS, PGA, 883C; LEV B FULLY COMPLIANT(EEPROM) |
| 中文描述： | Am42BDS6408G -堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁(yè)數(shù)： | 51/73頁(yè) |
| 文件大?。?/td> | 1080K |
| 代理商： | AM42BDS6408G |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)當(dāng)前第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)
50
Am42BDS6408G
November 1, 2002
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase/Program Operations
Notes:
1. Not 100% tested.
2. In asynchronous timing, addresses are latched on the falling edge of WE#. In synchronous mode, addresses are latched on the
first of either the rising edge of AVD# or the active edge of CLK.
3. See the “Flash Erase And Programming Performance” section for more information.
4. Does not include the preprogramming time.
Parameter
Description
All Speed
Options
Unit
JEDEC
Standard
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
80
ns
t
AVWL
t
AS
Address Setup Time
(Note 2)
Synchronous
Min
5
ns
Asynchronous
0
t
WLAX
t
AH
Address Hold Time
(Note 2)
Synchronous
Min
7
ns
Asynchronous
45
t
ACS
t
ACH
t
DS
t
DH
t
GHWL
t
CAS
t
CH
t
WP
t
WPH
t
SR/W
t
WHWH1
t
WHWH1
Address Setup Time to CLK (Note 2)
Min
5
ns
Address Hold Time to CLK (Note 2)
Min
7
ns
t
DVWH
t
WHDX
t
GHWL
Data Setup Time
Min
45
ns
Data Hold Time
Min
0
ns
Read Recovery Time Before Write
Min
0
ns
CE# Setup Time to AVD#
Min
0
ns
t
WHEH
t
WLWH
t
WHWL
CE# Hold Time
Min
0
ns
Write Pulse Width
Min
50
ns
Write Pulse Width High
Min
30
ns
Latency Between Read and Write Operations
Min
0
ns
t
WHWH1
t
WHWH1
Programming Operation (Note 3)
Typ
8
μs
Accelerated Programming Operation (Note 3)
Typ
2.5
μs
t
WHWH2
t
WHWH2
Sector Erase Operation (Notes 3, 4)
Typ
0.2
sec
Chip Erase Operation (Notes 3, 4)
26.8
t
VID
t
VIDS
t
VCS
t
CSW1
t
CSW2
t
CHW
t
CS
t
AVSW
t
AVHW
t
AVHC
t
AVDP
V
ACC
Rise and Fall Time
V
ACC
Setup Time (During Accelerated Programming)
V
CC
Setup Time
Clock Setup Time to WE# (Asynchronous)
Min
500
ns
Min
1
μs
Min
50
μs
Min
5
ns
Clock Setup Time to WE# (Synchronous)
Min
1
ns
Clock Hold Time from WE#
Min
1
ns
t
ELWL
CE# Setup Time to WE#
Min
0
ns
AVD# Setup Time to WE#
Min
5
ns
AVD# Hold Time to WE#
Min
5
ns
AVD# Hold Time to CLK
Min
5
ns
AVD# Low Time
Min
12
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM42DL16X2D | 150NS, CERDIP, 883C; LEV B COMPLIANT(EEPROM) |
| AM42DL16X4D | 150NS, PLCC, IND TEMP(EEPROM) |
| AM42DL32X4G | 150NS, 32LCC, 883C; LEV B COMPLIANT(EEPROM) |
| AM42DL6402G | 150NS, SOIC, IND TEMP(EEPROM) |
| AM42DL6404G | 64 Mbit (8 M x 8-Bit/4 M x 16-Bit) CMOS and 4 Mbit (256 K x 16-Bit) Static RAM (Preliminary) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM42BDS6408GBD8IT | 制造商:Spansion 功能描述:COMBO 4MX16 FLASH + 512KX16 SRAM 1.8V 93FBGA - Tape and Reel |
| AM42BDS6408GTD8I | 制造商:Spansion 功能描述:Combo Mem 4Mx16 Flash + 512Kx16 SRAM 1.8V 93-Pin FBGA |
| AM42BDS6408H | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory, and 8 Mbit (512 K x 16-Bit) SRAM |
| AM42BDS6408HD3I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory, and 8 Mbit (512 K x 16-Bit) SRAM |
| AM42BDS6408HD4I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory, and 8 Mbit (512 K x 16-Bit) SRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。