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| 型號(hào)： | AM42BDS6408G |
| 英文描述： | 250NS, PGA, 883C; LEV B FULLY COMPLIANT(EEPROM) |
| 中文描述： | Am42BDS6408G -堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁(yè)數(shù)： | 55/73頁(yè) |
| 文件大?。?/td> | 1080K |
| 代理商： | AM42BDS6408G |
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54
Am42BDS6408G
November 1, 2002
P R E L I M I N A R Y
AC CHARACTERISTICS
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid
Address for reading status bits.
2. “In progress” and “complete” refer to status of program
operation.
3. A21–A12 are don’t care during command sequence
unlock cycles.
4. Addresses are latched on the first of either the rising edge
of AVD# or the active edge of CLK.
5. Either CS# or AVD# is required to go from low to high in
between programming command sequences.
6. The Synchronous programming operation is independent
of the Set Device Read Mode bit in the Burst Mode
Configuration Register.
7. AVD# must toggle during command sequence unlock cy-
cles.
8. t
AH
= 45 ns.
9. CLK must not have an active edge while WE# is at V
IL
.
Figure 24.
Alternate Synchronous Program Operation Timings
OE#
CE#
Data
Addresses
AVD#
WE#
CLK
V
CC
555h
PD
t
AH
t
WC
t
WPH
t
WP
PA
t
VCS
t
DH
t
CH
In
Progress
t
WHWH1
VA
Complete
VA
Program Command Sequence (last two cycles)
Read Status Data
t
DS
t
AVDP
A0h
t
ACS
t
CAS
t
ACH
t
AVCH
t
CSW2
t
AS
(Note 8)
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