參數(shù)資料
型號: AM42BDS6408G
英文描述: 250NS, PGA, 883C; LEV B FULLY COMPLIANT(EEPROM)
中文描述: Am42BDS6408G -堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁數(shù): 43/73頁
文件大?。?/td> 1080K
代理商: AM42BDS6408G
42
Am42BDS6408G
November 1, 2002
P R E L I M I N A R Y
AC CHARACTERISTICS
Notes:
1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active falling edge.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
4. A17 = 0.
Figure 12.
CLK Synchronous Burst Mode Read
(Falling Active Clock)
Da
Da + 1
Da + n
OE#
DQ15
-
DQ0
A21
-
A0
Aa
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVC
t
AVD
t
ACH
t
OE
t
OEZ
t
CEZ
t
IACC
t
ACC
t
BDH
4 cycles for initial access shown.
t
RACC
Hi-Z
Hi-Z
Hi-Z
1
2
3
4
5
t
RDYS
t
BACC
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