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參數(shù)資料
| 型號(hào)： | AM42BDS6408G |
| 英文描述： | 250NS, PGA, 883C; LEV B FULLY COMPLIANT(EEPROM) |
| 中文描述： | Am42BDS6408G -堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁數(shù)： | 62/73頁 |
| 文件大?。?/td> | 1080K |
| 代理商： | AM42BDS6408G |
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November 1, 2002
Am42BDS6408G
61
P R E L I M I N A R Y
AC CHARACTERISTICS
Wait State Decoding Addresses:
A14, A13, A12 = “101”
5 programmed, 7 total
A14, A13, A12 = “100”
4 programmed, 6 total
A14, A13, A12 = “011”
3 programmed, 5 total
A14, A13, A12 = “010”
2 programmed, 4 total
A14, A13, A12 = “001”
1 programmed, 3 total
A14, A13, A12 = “000”
0 programmed, 2 total
Note:
Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”.
Figure 32.
Example of Wait States Insertion (Standard Handshaking Device)
Data
AVD#
OE#
CLK
1
2
3
4
5
D0
D1
0
1
6
2
7
3
total number of clock cycles
following AVD# falling edge
Rising edge of next clock cycle
following last wait state triggers
next burst data
number of clock cycles
programmed
4
5
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