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| 型號： | AM42BDS6408G |
| 英文描述： | 250NS, PGA, 883C; LEV B FULLY COMPLIANT(EEPROM) |
| 中文描述： | Am42BDS6408G -堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁數(shù)： | 18/73頁 |
| 文件大小： | 1080K |
| 代理商： | AM42BDS6408G |
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November 1, 2002
Am42BDS6408G
17
P R E L I M I N A R Y
Table 4.
System Interface String
Table 5.
Device Geometry Definition
19h
1Ah
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
Addresses
Data
Description
1Bh
0017h
V
CC
Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0019h
V
CC
Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
0000h
V
PP
Min. voltage (00h = no V
PP
pin present)
1Eh
0000h
V
PP
Max. voltage (00h = no V
PP
pin present)
1Fh
0004h
Typical timeout per single byte/word write 2
N
μs
20h
0000h
Typical timeout for Min. size buffer write 2
N
μ
s (00h = not supported)
21h
0009h
Typical timeout per individual block erase 2
N
ms
22h
0000h
Typical timeout for full chip erase 2
N
ms (00h = not supported)
23h
0004h
Max. timeout for byte/word write 2
N
times typical
24h
0000h
Max. timeout for buffer write 2
N
times typical
25h
0004h
Max. timeout per individual block erase 2
N
times typical
26h
0000h
Max. timeout for full chip erase 2
N
times typical (00h = not supported)
Addresses
Data
Description
27h
0017h
Device Size = 2
N
byte
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0000h
0000h
Max. number of bytes in multi-byte write = 2
N
(00h = not supported)
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0003h
0000h
0040h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
007Dh
0000h
0000h
0001h
Erase Block Region 2 Information
35h
36h
37h
38h
0003h
0000h
0040h
0000h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
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