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參數(shù)資料
| 型號： | ADSP-21mod970 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multi-Port Internet Gateway Processor(多口網(wǎng)關(guān)處理器) |
| 中文描述： | 多端口Internet網(wǎng)關(guān)處理器（多口網(wǎng)關(guān)處理器） |
| 文件頁數(shù)： | 7/50頁 |
| 文件大?。?/td> | 980K |
| 代理商： | ADSP-21MOD970 |
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ADSP-21mod970 Preliminary Data Sheet
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Preimnary
RESET only, while serial port pins are software configurable during program execution. Flag and
interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is
reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics.
Technca
Serial Ports
The ADSP-21mod970 has a multichannel serial port (SPORT) connected to each internal digital modem
processor for serial communications.
Here is a brief list of the capabilities of the ADSP-21mod970 SPORT. For additional information on the
internal Serial Ports, refer to the
ADSP-2100 Family User’s Manual
.
SPORT is bidirectional and has a separate, double-buffered transmit and receive section.
SPORT can use an external serial clock or generate its own serial clock internally.
SPORT has independent framing for the receive and transmit sections. Sections run in a
frameless mode or with frame synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of two pulse widths and tim-
ings.
SPORT supports serial data word lengths from 3 to 16 bits and provides optional A-law
and μ-law companding according to CCITT recommendation G.711.
SPORT receive and transmit sections can generate unique interrupts on completing a data
word transfer.
SPORT can receive and transmit an entire circular buffer of data with one overhead cycle
per data word. An interrupt is generated after a data buffer transfer.
A multichannel interface selectively receives and transmits a 24 or 32 word, time-division
multiplexed, serial bitstream.
Pin Descriptions
The ADSP-21mod970 is available in a 304-lead PBGA package. In order to maintain maximum
functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and
external bus pins have dual, multiplexed functionality. The external bus pins are configured during
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