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參數(shù)資料
| 型號(hào)： | ADSP-21mod970 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multi-Port Internet Gateway Processor(多口網(wǎng)關(guān)處理器) |
| 中文描述： | 多端口Internet網(wǎng)關(guān)處理器（多口網(wǎng)關(guān)處理器） |
| 文件頁數(shù)： | 20/50頁 |
| 文件大?。?/td> | 980K |
| 代理商： | ADSP-21MOD970 |
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ADSP-21mod970 Preliminary Data Sheet
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The ADSP-2100 Family development software (Revision 5.02 and later) fully supports the BDMA
booting feature and can generate byte memory space compatible boot code.
Technca
transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is generated. The
BMPAGE and BEAD registers must not be accessed by the processor during BDMA operations.
The source or destination of a BDMA transfer will always be on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value the BDMA circuit starts executing byte
memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero.
When enough accesses have occurred to create a destination word, it is transferred to or from on-chip
memory. The transfer takes one processor cycle. Processor accesses to external memory have priority
over BDMA byte memory accesses.
The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA
accesses are occurring. Setting the BCR bit to 0 allows the processor to continue operations. Setting the
BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear the
context of the processor, and start execution at address 0 when the BDMA accesses have completed. The
BDMA overlay bits specify the OVLAY memory blocks to be accessed for internal memory.
Bootstrap Loading (Booting)
The ADSP-21mod970 has two mechanisms to allow automatic loading of the internal program memory
after reset. The method for booting is controlled by the Mode A, B, and C configuration bits. When the
MODE pins specify BDMA booting, the ADSP-21mod970 initiates a BDMA boot sequence when reset
is released.
The BDMA interface is set up during reset to the following defaults when BDMA booting is specified:
the BDIR, BMPAGE, BIAD, and BEAD registers are set to 0, the BTYPE register is set to 0 to specify
program memory 24 bit words, and the BWCOUNT register is set to 32. This causes 32 words of on-
chip program memory to be loaded from byte memory. These 32 words are used to set up the BDMA to
load in the remaining program code. The BCR bit is also set to 1, which causes program execution to be
held off until all 32 words are loaded into on-chip program memory. Execution then begins at address 0.
The IDLE instruction can also be used to allow the processor to hold off execution while booting
continues through the BDMA interface. For BDMA accesses while in Host Mode, the addresses to boot
memory must be constructed externally to the ADSP-21mod970. The only memory address bit provided
by the processor is A0.
Composite Memory Select (CMS)
The ADSP-21mod970 has a programmable memory select signal that is useful for generating memory
select signals for memories mapped to more than one space. The CMS signal is generated to have the
same timing as each of the individual memory select signals (PMS, DMS, BMS, IOMS) but can combine
their functionality.
Each bit in the CMSSEL register, when set, causes the CMS signal to be asserted when the selected
memory select is asserted. For example, to use a 32K word memory to act as both program and data
memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select
of the memory, and use either DMS or PMS as the additional address bit.
The CMS pin functions like the other memory select signals with the same timing and bus request logic.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21MOD970-000 | 制造商:Analog Devices 功能描述: |
| ADSP-21MOD980-000 | 制造商:Analog Devices 功能描述: |
| ADSP21MOD980N | 制造商:AD 制造商全稱:Analog Devices 功能描述:MultiPort Internet Gateway Processor |
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| adsp-21msp50akg-52 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
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